Patents Assigned to Advanced Semiconductor Engineering, Inc.
  • Semiconductor device package including stress buffering layer
    Patent number: 11721678
    Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
  • ELECTRONIC DEVICE
    Publication number: 20230244049
    Abstract: The present disclosure relates to an electronic device that includes a waveguide, a plurality of transceiving portions over the waveguide, and a cavity between the waveguide and the transceiving portions and connecting the waveguide with the transceiving portions. The cavity is configured for resonating of an electromagnetic wave from the waveguide or the transceiving portions.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 3, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-I WU, Ming-Fong JHONG
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20230245963
    Abstract: A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 3, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chang-Lin YEH
  • Electronic device, package structure and electronic manufacturing method
    Patent number: 11715716
    Abstract: An electronic device, a package structure and an electronic manufacturing method are provided. The electronic device includes a substrate, a first bump, a second bump and a first reflowable material. The first bump is disposed over the substrate, and has a first width. An end portion of the first bump defines a first recess portion. The second bump is disposed over the substrate, and has a second width less than the first width. The first reflowable material is disposed on the first bump and extends in the first recess portion.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: August 1, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Pei-Jen Lo
  • Embedded component package structure having a magnetically permeable layer
    Patent number: 11715694
    Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: August 1, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsing Kuo Tien, Chih Cheng Lee
  • Device for communication
    Patent number: 11714243
    Abstract: A device is provided. The device may be an optical device, a light coupling device, or a device containing an optical structure. The device includes a waveguide, a cladding, and a light coupling material. The light coupling material is disposed adjacent to the waveguide and has a first surface and a second surface, where the second surface is disposed further away from the waveguide than the first surface and a thickness of the second surface is greater than that of the first surface.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 1, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jr-Wei Lin, Sin-Yuan Mu, Mei-Ju Lu
  • ELECTRONIC DEVICE
    Publication number: 20230240057
    Abstract: An electronic device is disclosed. The electronic device includes a first electronic component, a first power regulator disposed above the first electronic component. The first power regulator is configured to receive a first power along a lateral surface of the first electronic component without passing the first electronic component and to provide a second power to the first electronic component. The electronic device also includes a passive component disposed in an electrical path between the first electronic component and the first power regulator.
    Type: Application
    Filed: January 26, 2022
    Publication date: July 27, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Chieh HUNG, Chen-Chao WANG
  • Semiconductor device package and method of manufacturing the same
    Patent number: 11710689
    Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: July 25, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Lin Yeh, Yu-Chang Chen
  • Package structure and method for manufacturing the same
    Patent number: 11710675
    Abstract: A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: July 25, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • ELECTRONIC PACKAGE AND ELECTRONIC DEVICE
    Publication number: 20230230966
    Abstract: The present disclosure provides an electronic package. The electronic package includes a substrate, a first component disposed on the substrate and configured to detect an external signal, and an encapsulant disposed on the substrate. The electronic package also includes a protection element disposed on the substrate and physically separating the first device from the encapsulant and exposing the first device. The present disclosure also provides an electronic device.
    Type: Application
    Filed: January 14, 2022
    Publication date: July 20, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Hao CHANG
  • METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE
    Publication number: 20230230953
    Abstract: A method for manufacturing a semiconductor package structure is provided. The method includes: (a) providing a semiconductor structure including a first device and a second device; (b) irradiating the first device by a first energy-beam with a first irradiation area; and (c) irradiating the first device and the second device by a second energy-beam with a second irradiation area greater than the first irradiation area of the first energy-beam.
    Type: Application
    Filed: March 20, 2023
    Publication date: July 20, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yi Dao WANG, Tung Yao LIN, Rong He GUO
  • Semiconductor package structure and method for manufacturing the same
    Patent number: 11705401
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate and a first passive device. The substrate has a first surface and a second surface opposite to the first surface. The first passive device includes a first terminal and a second terminal, wherein the first terminal is closer to the first surface than to the second surface, and the second terminal is closer to the second surface than to the first surface.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: July 18, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt, Kay Stefan Essig
  • Device package
    Patent number: 11705412
    Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: July 18, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Nan Lin, Wei-Tung Chang, Jen-Chieh Kao, Huei-Shyong Cho
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230223354
    Abstract: A semiconductor device package includes a substrate having a surface, a conductive element disposed on the surface of the substrate, and an encapsulant disposed on the surface of the substrate and covering the conductive element. The conductive element has an upper surface facing away from the substrate and exposed from the encapsulant. Further, a roughness of the upper surface of the conductive element is greater than a roughness of a side surface of the conductive element.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 13, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei Da LIN, Meng-Jen WANG, Hung Chen KUO, Wen Jin HUANG
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230223676
    Abstract: A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.
    Type: Application
    Filed: March 7, 2023
    Publication date: July 13, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin HO, Chih-Cheng LEE, Chun Chen CHEN, Yuanhao YU
  • SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20230223352
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.
    Type: Application
    Filed: March 14, 2023
    Publication date: July 13, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Semiconductor device package and method of manufacturing the same
    Patent number: 11699682
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first module, a second module, a first intermediate circuit layer, a first conductive transmission path and a second conductive transmission path. The second module is stacked on the first module. The first intermediate circuit layer is arranged between the first module and the second module. The first conductive transmission is configured to electrically connect the first semiconductor module with the first intermediate circuit layer. The second conductive transmission path is configured to electrically connect the first intermediate circuit layer with the second semiconductor module.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: July 11, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Electronic device package and method of manufacturing the same
    Patent number: 11699654
    Abstract: An electronic device package includes an encapsulated electronic component, a redistribution layer (RDL) and a conductive via. The RDL is disposed above the encapsulated electronic component. The RDL includes a circuit layer comprising a conductive pad including a pad portion having a curved edge and a center of curvature, and an extension portion protruding from the pad portion and having a curved edge and a center of curvature. The circuit layer further includes a dielectric layer above the RDL. The conductive via is disposed in the dielectric layer and connected to the conductive pad of the RDL. A center of the conductive via is closer to the center of curvature of the edge of the extension portion than to the center of curvature of the edge of the pad portion.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: July 11, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-An Chen, Chih-Yi Huang, Ping Cing Shen
  • ELECTRONIC PACKAGE AND METHOD OF FORMING THE SAME
    Publication number: 20230215775
    Abstract: An electronic package is provided in the present disclosure. The electronic package comprises: an electronic component; a thermal conductive element above the electronic component, wherein thermal conductive element includes a first metal; an adhesive layer between the electronic component and the thermal conductive element, wherein the first adhesive layer includes a second metal; and an intermetallic compound (IMC) between the first metal and the second metal.
    Type: Application
    Filed: January 5, 2022
    Publication date: July 6, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chang-Lin YEH
  • ELECTRONIC PACKAGE STRUCTURE
    Publication number: 20230215790
    Abstract: An electronic package structure is provided. The electronic package structure includes a first carrier, a first electronic component, a first optical channel, and a second electronic component. The first electronic component is disposed on or within the first carrier. The first optical channel is disposed within the first carrier. The first optical channel is configured to provide optical communication between the first electronic component and the second electronic component. The first carrier is configured to electrically connect the first electronic component.
    Type: Application
    Filed: January 5, 2022
    Publication date: July 6, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chiung-Ying KUO, Hung-Chun KUO