Patents Assigned to Advanced Semiconductor Engineering, Inc.
  • SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20230145588
    Abstract: A semiconductor package includes a substrate, a preformed feeding element, a preformed shielding element, and an encapsulant. The preformed feeding element is disposed on the substrate and the preformed feeding element is disposed on the substrate and adjacent to the preformed feeding element. The encapsulant encapsulates the preformed feeding element and the preformed shielding element.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 11, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng Yuan CHEN, Jiming LI, Chun Chen CHEN, Yuanhao YU
  • METHOD AND SYSTEM FOR MANUFACTURING A SEMICONDUCTOR PACKAGE STRUCTURE
    Publication number: 20230138460
    Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Che-Ting LIU, Jheng-Yu HONG, Yu-Ting LU, Po-Chun LEE, Chih-Hsiang HSU
  • OPTOELECTRONIC PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230136046
    Abstract: An optoelectronic package structure is provided. The optoelectronic package structure includes a carrier and a photonic component. The carrier includes an upper surface and a first lateral surface. The photonic component is disposed over an upper surface of the carrier and includes an optical portion. The carrier includes a recessed portion recessed from the first lateral surface of the carrier, and the optical portion of the photonic component is located within the recessed portion of the carrier from a top view perspective.
    Type: Application
    Filed: October 28, 2021
    Publication date: May 4, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsiang-Cheng TSAI, Jui-Che WU
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230136049
    Abstract: The present disclosure provides a semiconductor device package including a first substrate and an adhesive layer. The first substrate has a first surface and a conductive pad adjacent to the first surface. The conductive pad has a first surface exposed from the first substrate. The adhesive layer is disposed on the first surface of the first substrate. The adhesive layer has a first surface facing the first substrate. The first surface of the adhesive layer is spaced apart from the first surface of the conductive pad in a first direction substantially perpendicular to the first surface of the first substrate. The conductive pad and the adhesive layer are partially overlapping in the first direction.
    Type: Application
    Filed: January 3, 2023
    Publication date: May 4, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Yi Chun CHOU
  • Semiconductor device packages including an inductor and a capacitor
    Patent number: 11637172
    Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: April 25, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Teck-Chong Lee
  • Semiconductor device package
    Patent number: 11637055
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface of the first substrate. The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface of the second substrate. The semiconductor device package also includes a first electronic component disposed on the first surface of the second substrate and electrically connected to the first surface of the second substrate. The semiconductor device package also includes a first encapsulant and a second encapsulant between the first substrate and the second substrate. The first encapsulant is different from the second encapsulant. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: April 25, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hua Tai, Wen-Pin Huang
  • ELECTRONIC PACKAGE STRUCTURE
    Publication number: 20230124000
    Abstract: At least some embodiments of the present disclosure relate to an electronic package structure. The electronic package structure includes an electronic structure, a wiring structure disposed over the electronic structure, a bonding element connecting the wiring structure and the electronic structure, and a reinforcement element attached to the wiring structure. An elevation difference between a highest point and a lowest point of a surface of the wiring structure facing the electronic structure is less than a height of the bonding element.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 20, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Jen WANG, Po-Jen CHENG, Fu-Yuan CHEN, Yi-Hsin CHENG
  • ELECTRONIC PACKAGE STRUCTURE
    Publication number: 20230124933
    Abstract: An electronic package structure includes an electronic structure, a wiring structure, an electrical contact and a support layer. The wiring structure is located over the electronic structure. The electrical contact connects the wiring structure and the electronic structure. The support layer is disposed around the electrical contact and has a surface facing the electrical contact. The surface includes at least one inflection point in a cross-sectional view.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 20, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Jen WANG, Po-Jen CHENG, Fu-Yuan CHEN
  • OPTOELECTRONIC PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230120036
    Abstract: An optoelectronic package structure is provided. The optoelectronic package includes a carrier, an electronic component, a photonic component and a first power supply path in the carrier. The carrier includes a first region and the electronic component is disposed over the first region of the carrier. A first power supply path is electrically connects the electronic component.
    Type: Application
    Filed: October 20, 2021
    Publication date: April 20, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Mei-Ju LU
  • OPTOELECTRONIC PACKAGE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20230122292
    Abstract: An optoelectronic package includes an input/output (I/O) component, a photonic component, and an electronic component configured to modulate optical signals in the photonic component. The I/O component is electrically connected to the photonic component via the electronic component.
    Type: Application
    Filed: October 20, 2021
    Publication date: April 20, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Mei-Ju LU, Jung Jui KANG
  • OPTOELECTRONIC PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20230121954
    Abstract: An optoelectronic package structure is provided. The optoelectronic package structure includes a heat source, a thermal conductive element, and a first optoelectronic component and a second optoelectronic component. The thermal conductive element is disposed over the heat source. The thermal conductive element defines a thermal conduction path P2 by which heat is transferred from the heat source to the thermal conductive element. The first optoelectronic component and the second optoelectronic component are arranged along an axis different from a thermal conduction path P2.
    Type: Application
    Filed: October 15, 2021
    Publication date: April 20, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jr-Wei LIN, Mei-Ju LU
  • ANTENNA DEVICE
    Publication number: 20230123962
    Abstract: The present disclosure provides an antenna device. The antenna device includes a dielectric element including a first region and a second region, a first antenna disposed on the first region, and a second antenna disposed on the second region. The first antenna and the second antenna are configured to operate in different frequencies. The first antenna and the second antenna are misaligned in directions perpendicular and parallel to a surface of the dielectric element on which the first antenna or the second antenna is disposed.
    Type: Application
    Filed: October 15, 2021
    Publication date: April 20, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Mark GERBER
  • Vertical capacitor structure having capacitor in cavity, and method for manufacturing the vertical capacitor structure
    Patent number: 11631734
    Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: April 18, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Syu-Tang Liu, Huang-Hsien Chang, Tsung-Tang Tsai, Hung-Jung Tu
  • Substrate structure, semiconductor package structure and method for manufacturing semiconductor package structure
    Patent number: 11631633
    Abstract: A substrate structure and a semiconductor package structure including the same are provided. The substrate structure includes a circuit layer and a dielectric structure. The circuit layer has a bottom surface and a top surface opposite to the bottom surface. The dielectric structure around the circuit layer. The dielectric structure covers a first part of the bottom surface of the circuit layer, and exposes a second part of the bottom surface and the top surface of the circuit layer. The dielectric structure exposes the top surface of the circuit layer. In addition, a method of manufacturing a semiconductor package structure is also provided.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: April 18, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Kuang-Hsiung Chen, Bernd Karl Appelt
  • Semiconductor device including via structure for vertical electrical connection
    Patent number: 11631631
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, a conductive structure and at least one via structure. The conductive structure is disposed on an upper surface of the semiconductor substrate. The at least one via structure is disposed in the semiconductor substrate. A portion of the at least one via structure extends beyond the conductive structure.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: April 18, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chin-Cheng Kuo
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230114278
    Abstract: A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a first substrate, a second substrate and an interconnection. The second substrate is arranged above the first substrate and has an opening. The interconnection passes through the opening and connects to the first substrate and the second substrate.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chao Wei LIU
  • ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230115954
    Abstract: An electronic device package and manufacturing method thereof are provided. The electronic device package includes an electronic component including an active surface, a patterned conductive layer disposed on the active surface, an encapsulation layer disposed over the patterned conductive layer, and a buffer layer disposed between the patterned conductive layer and the encapsulation layer. The buffer layer is shaped and sized to alleviate a stress generated due to an interaction between the patterned conductive layer and the encapsulation layer.
    Type: Application
    Filed: October 13, 2021
    Publication date: April 13, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: En Hao HSU, Kuo Hwa TZENG, Chia-Pin CHEN, Chi Long TSAI
  • Package structure and method for manufacturing the same
    Patent number: 11626525
    Abstract: A package structure is provided. The package structure includes a substrate, a sensor device, an encapsulant and a signal blocking structure. The substrate has a signal passing area. The sensor device is disposed over the substrate. The sensor device has a first surface, a second surface opposite to the first surface and a sensing area located at the second surface. The second surface of the sensor device faces the substrate. The encapsulant covers the sensor device and the substrate. The signal blocking structure extends from the substrate into the encapsulant.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: April 11, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun Yu Ko, Tsu-Hsiu Wu, Meng-Jen Wang
  • Optical module
    Patent number: 11626441
    Abstract: An optical module includes an image sensor and micro lens array. The image sensor has at least one group of pixels. The micro lens array is disposed on the image sensor. The at least one group of pixels is shifted from the micro lens array in a first direction from a top view perspective.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: April 11, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsin-Ying Ho
  • Semiconductor device package and method for manufacturing the same
    Patent number: 11626360
    Abstract: A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: April 11, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chang-Lin Yeh