Patents Assigned to ADVANCED
  • Patent number: 12255098
    Abstract: A carrier substrate includes a base layer, an antireflection layer, and an energy absorption layer, wherein the antireflection layer is formed on one surface of the base layer and allows an elastic wave generated by a first laser beam transmitted through an element adhesively bonded to the antireflection layer to be transmitted through the base layer without being reflected towards the element, the first laser beam being applied to the element through a source substrate of the element, and the energy absorption layer is formed between the base layer and the antireflection layer to be aligned with the element, and evaporates upon energy absorption.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: March 18, 2025
    Assignee: CENTER FOR ADVANCED META-MATERIALS
    Inventors: Jae Hyun Kim, Jae Gu Kim, Sang Min Kim, Kwang Seop Kim, Yun Hwangbo, Hak Joo Lee, Se Jeong Won
  • Patent number: 12254527
    Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: March 18, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Timour T. Paltashev, Michael Mantor, Rex Eldon McCrary
  • Patent number: 12253961
    Abstract: Staging memory access requests includes receiving a memory access request directed to Dynamic Random Access Memory; storing the memory access request in a staging buffer; and moving the memory access request from the staging buffer to a command queue.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 18, 2025
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: James R. Magro, Kedarnath Balakrishnan, Ravindra N. Bhargava, Guanhao Shen
  • Patent number: 12254858
    Abstract: Disclosed herein is an acoustic metamaterial structure which can effectively reduce noise in a specific frequency range through formation of an acoustic bandgap, wherein the specific frequency range is determined by a periodic structure formed by an array of multiple unit cells. The acoustic metamaterial structure includes multiple first unit cells each including a first space having a first cross-sectional area and a second space disposed downstream of the first space in a flow direction of fluid to communicate with the first space, the second space having a second cross-sectional area larger than the first cross-sectional area, wherein the acoustic metamaterial structure reduces noise in a specific frequency range through formation of an acoustic bandgap, the specific frequency range being determined by a periodic structure formed by an array of the first space and the second space.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: March 18, 2025
    Assignee: CENTER FOR ADVANCED META-MATERIALS
    Inventors: Jong Jin Park, Jae Hwa Lee, Eun Bok, Hak Joo Lee
  • Patent number: 12253892
    Abstract: Package lids with carveouts configured for processor connection and alignment are described. Lid carveouts are configured to align and mechanically secure a cooling device to the package lid by receiving protrusions of the cooling device. Because the lid carveouts ensure precise alignment and orientation of a cooling device relative to a package lid, the lid design enables targeted cooling of discrete portions of the lid. Lid carveouts are further configured to expose one or more connectors disposed on a surface that supports package internal components. When contacted by corresponding connectors of a cooling device, the lid carveouts enable direct connections between the package and the attached cooling device. By creating a direct connection between package components and an attached cooling device, the lid carveouts enable a high-speed connection for proactive and on-demand cooling actuation.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: March 18, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jerry Anton Ahrens, William Robert Alverson, Amitabh Mehra, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
  • Patent number: 12254217
    Abstract: Systems, apparatuses, and methods for dynamically coalescing multi-bank memory commands to improve command throughput are disclosed. A system includes a processor coupled to a memory via a memory controller. The memory also includes processing-in-memory (PIM) elements which are able to perform computations within the memory. The processor generates memory requests targeting the memory which are sent to the memory controller. The memory controller stores commands received from the processor in a queue, and the memory controller determines whether opportunities exist for coalescing multiple commands together into a single multi-bank command. After coalescing multiple commands into a single combined multi-bank command, the memory controller conveys, across the memory bus to multiple separate banks, the single multi-bank command and a multi-bank code specifying which banks are targeted. The memory banks process the command in parallel, and the PIM elements process the data next to each respective bank.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: March 18, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Johnathan Alsop, Shaizeen Dilawarhusen Aga
  • Patent number: 12252165
    Abstract: The invention provides railroad path optimization method. The method determines whether at least one switch machine from a plurality of switch machines is occupied in the at least one route and detects at least one unavailable route if the at least one switch machine is occupied. Further, the method identifies at least one desired route and at least one available route associated with an origin point and at least one desired route and at least one available route associated with a destination point to identify at least one available route for the destination point. Based on the identified available route, the method predicts the at least one optimal route and ranks the at least one predicted optimal route to enable selection of a final optimal route for travel.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: March 18, 2025
    Assignee: Advanced Rail Systems
    Inventors: John Michael Minor, Gustavo Vargas
  • Patent number: 12254353
    Abstract: In order to efficiently process graphics data, operations are performed including allocating a first set of resource slots for a first execution instance of a pipeline shader program; correlating the first set of resource slots with graphics pipeline passes; and on a second execution instance of the pipeline shader program, assigning resource slots, from the first set of resource slots, to the graphics pipeline passes, based on the correlating.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: March 18, 2025
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Zhuo Chen, Steven J. Tovey
  • Patent number: 12254807
    Abstract: A pixel circuit in a display panel includes a drive transistor, a first terminal of the drive transistor is electrically connected to a power signal line; and drive modes of the display panel comprise at least a first drive mode, a second drive mode, and a third drive mode, wherein the first drive mode corresponds to a first drive frequency F1 and a first power signal Vdd1, the second drive mode corresponds to a second drive frequency F2 and a second power signal Vdd2, and the third drive mode corresponds to a third drive frequency F3 and a third power signal Vdd3, wherein F 1 > F 2 > F 3 , F 2 - F 3 F 1 - F 3 ? ? "\[LeftBracketingBar]" V dd ? 2 - V dd ? 3 ? "\[RightBracketingBar]" ? "\[LeftBracketingBar]" V dd ? 1 - V dd ? 3 ? "\[RightBracketingBar]" .
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: March 18, 2025
    Assignee: Hubei Yangtze Industrial Innovation Center Of Advanced Display Co., Ltd.
    Inventor: Jujian Fu
  • Patent number: 12252630
    Abstract: The present application relates to a conductive structure formed by connecting a modified graphene oxide or modified carbon nanotube with a conductive polymer, and an antistatic composition including the same. The antistatic composition of the present application has advantages of an excellent adhesive property, improved surface roughness, mechanical strength, and improved electrical properties.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: March 18, 2025
    Assignee: DAEJIN ADVANCED MATERIALS INC.
    Inventors: Gwan Yeong Kim, Gi Moon Yoo
  • Patent number: 12254195
    Abstract: Sparse matrix operations using processing-in-memory is described. In accordance with the described techniques, a processing-in-memory component of a memory module receives a request for a vector element stored at a first location in memory of the memory module. The processing-in-memory component identifies an index value for a non-zero element in a sparse matrix using a representation of the sparse matrix stored at a second location in the memory. The processing-in-memory component then outputs a result that includes the vector element by retrieving the vector element from the first location in memory using the index value.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: March 18, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Matthew R Poremba
  • Patent number: 12255048
    Abstract: An apparatus and method to produce a waveform. The apparatus includes a first node to couple to a substrate support and a power supply coupled to a second node wherein the power supply is configured to provide a DC voltage to set an ion-energy at a surface of the substrate. The apparatus also includes a first switch that couples the second node to the first node, and responsive to the first switch being closed, a first voltage is applied at the first node. A second switch of the power supply couples a third node to the first node, and responsive to the second switch being closed, a second voltage is applied at the first node to effectuate a negative voltage at the surface of the substrate.
    Type: Grant
    Filed: October 26, 2023
    Date of Patent: March 18, 2025
    Assignee: Advanced Energy Industries, Inc.
    Inventors: Victor Brouk, Randy Heckman
  • Patent number: 12251689
    Abstract: The present invention relates to a catalyst composition comprising a gold nanoparticle superlattice embedded in hierarchical porous silica and a method for manufacturing the same. The catalyst composition comprising a gold nanoparticle superlattice embedded in hierarchical porous silica according to the present invention comprises micropores and mesopores in the superlattice, so that these pores are channelized to allow the rapid access of reactants to surfaces of gold nanoparticles, and the catalyst composition is very structurally stable and has excellent catalytic activity, and thus has an effect of exhibiting a CO conversion rate of 100% at room temperature.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: March 18, 2025
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Sung Min Choi, Shin Hyun Kang
  • Patent number: 12254196
    Abstract: Systems, apparatuses, and methods for moving data from a memory in a computing system to an I/O device. A system includes a processor, memory, I/O controller, and power management circuitry. An application stores data in the memory that is to be ultimately conveyed to an I/O device. The I/O controller is configured to convey the data to an I/O device according to a service interval. The I/O controller is configured to fetch a first data item from the memory stored by the application, and prefetch one or more additional data items from memory. The first data and prefetched data are stored in a locally accessible buffer of the I/O controller. The I/O controller is then configured to convey each of the first data and one or more data items from the buffer to the I/O device at regular intervals of time during a given period of time, prior to initiating a fetch of additional data from the memory.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: March 18, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Raul Gutierrez
  • Patent number: 12253202
    Abstract: A fluid silencer includes: an expansion pipe disposed on a pipe through which a fluid containing noise sources flows and having an accommodation space therein; a viscous fluid received in the accommodation space; a noise introducing member disposed between the pipe and the expansion pipe to seal the accommodation space and allowing the noise sources to be introduced into the accommodation space therethrough; at least one partition member disposed in the accommodation space and dividing the accommodation space in a flow direction of the fluid; multiple baffle members disposed on one surface of the partition member and forming multiple sound absorbing spaces into which the noise sources introduced into the accommodation space are dispersedly introduced; and an elastic member disposed between the partition member and the baffle members and contracted/expanded by the viscous fluid entering/leaving the sound absorbing spaces as the noise sources are introduced into the sound absorbing spaces.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 18, 2025
    Assignee: CENTER FOR ADVANCED META-MATERIALS
    Inventors: Jong Jin Park, Jun Hyuk Kwak, Hak Joo Lee, Tae In Choi, Min Seok Jung
  • Patent number: 12252842
    Abstract: An energy dissipating fiber and fabric for protective textile application, which can absorb energy during shocking, stretching and vibration. The disclosed fiber/fabric can include a polymer matrix, a shear-thickening material and a reinforcing filler.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: March 18, 2025
    Assignee: Nano and Advanced Materials Institute Limited
    Inventors: Kang Zhang, Christopher Cheung Yec, Jian Zhang, Shilong Zhang, Xiyao Zhang, Jifan Li
  • Publication number: 20250089356
    Abstract: A change in switching time due to temperature change is suppressed. A switching circuitry is provided with a resistance component having opposite characteristics to temperature dependence of a gate current of a power transistor which is switching-controlled by the switching circuitry, and a change in a gate current due to the temperature change is suppressed by a change in the above-described resistance component due to the temperature change.
    Type: Application
    Filed: October 25, 2024
    Publication date: March 13, 2025
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Atsushi YAO, Mitsuo OKAMOTO, Fumiki KATO, Hiroshi SATO, Shinsuke HARADA, Hiroshi HOZOJI, Shinji SATO
  • Publication number: 20250086311
    Abstract: A data processing estimating method for privacy protection using a statistical estimation block design and a system for performing the method is disclosed. A data processing estimating system for privacy protection includes a block design unit for designing block designs for statistical estimation shared between data providers and data users; a modification data generating unit for generating modification data in a random manner along a conditional distribution for the original data of the above statistical estimation block design; and a data distribution estimating unit for estimating the distribution of the original data using an estimation function based on the statistical estimation block design.
    Type: Application
    Filed: April 29, 2024
    Publication date: March 13, 2025
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Si-Hyeon LEE, Hyunyoung PARK, Seung-Hyun NAM
  • Publication number: 20250082583
    Abstract: A microcapsule and a preparation method and use thereof are provided. The microcapsule includes a core phase and a shell phase with a volume ratio of (3.4-3.8):(0.8-1.2); wherein the core phase includes 8 wt % to 12 wt % of PVA, 4 wt % to 6 wt % of a density enhancer, 0.1 wt % to 0.3 wt % of an active substance, and a residual amount of water; the shell phase includes an elastomer precursor, a curing agent and silicone oil with a mass ratio of (9-11):(0.8-1.2):(2.5-3). The microcapsules of the present invention release active ingredients completely in milliseconds, and the release process exerts a relatively strong mechanical stimulation intensity on the surrounding environment which can further improve an absorption efficiency to the active ingredients in the fields of pharmaceuticals and cosmetics, and can provide a unique sensual experience in the field of food.
    Type: Application
    Filed: November 8, 2023
    Publication date: March 13, 2025
    Applicants: INFINITUS (CHINA) COMPANY LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Meiling TAI, Wanzhao LI, Shin-Hyun KIM, Wahyu Martumpal HAMONANGAN
  • Publication number: 20250088193
    Abstract: A method for driver calibration in die-to-die interfaces can include calibrating a delay lock loop of a delay line unit cell, by at least one processor, based on drive and load conditions of one or more driver unit cells of a physical layer of a die-to-die interconnect. The method can additionally include generating a clock signal, by the at least one processor, based on the delay lock loop. The method can further include communicating data, by the at least one processor, over the die-to-die interconnect based on the clock signal. Various other methods and systems are also disclosed.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 13, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Srikanth Reddy Gruddanti, Debasish Dwibedy, Manoj N. Kulkarni, Prasant Kumar Vallur, Priyadarshi Saxena