Abstract: A system may include a memory configured to store data of a first logic state in a ferroelectric capacitor when an electric polarization of the ferroelectric capacitor is in a first direction. A system may include a controller configured to erase the data from the memory by commanding the electric polarization of the ferroelectric capacitor in a second direction, opposite of the first direction and skipping a subsequent write operation of a null value to the memory.

Abstract: A parallel processor assigns data for use by one or more tasks to a shared memory or memories associated with a plurality of compute units. A scheduler or other controller within or otherwise associated with the parallel processor assigns threads or groups of threads, which utilize the assigned data, to compute units as appropriate. Compute units utilize two sets of instructions, one specifying upper bits and one specifying lower bits of a memory address, to specify memory addresses that are larger than a number of bits an individual instruction can specify in a memory address field. Mode setting commands determine when and how lower bits in a memory address field of an instruction will be combined with upper bits in a previous instruction, e.g., through concatenation.

Abstract: Hardware processor-based data compression includes subdividing source data into a plurality of partitions. A partition size for the subdividing is selected based on a search window size of a compression technique and a cache size of the hardware processor. A number of the plurality of partitions is selected based, at least in part, on a size of the source data and the partition size. Compressed data is generated by the hardware processor by performing multi-threaded compression in which a plurality of threads execute the compression technique on the plurality of partitions in parallel. Some aspects include prepending a random-access point (RAP) metadata frame by multi-threaded compression at a start of the plurality of partitions to enable the multi-threaded and parallel decompression. The RAP metadata frame is interpretable to enable single-threaded decompression by legacy decompressors.

Abstract: A method, system, and computer-readable medium for executing a task is disclosed. The method includes receiving input data and computing instructions, launching a workgroup including wavefronts to execute the task, wherein the launching causes the wavefronts to process the input data by sharing intermediate results and resources, and adjusting the operation based on characteristics of the wavefronts. The characteristics include data dependencies, computational load, memory usage, and execution timing requirements. The wavefronts execute the task in stages, where each stage processes portions of input data and data generated by other wavefronts.

Abstract: Data integrity checks for reducing communication latency is described. A transmitting endpoint transmits data to a receiving endpoint by generating an integrity tag for a first subset of data blocks and a second integrity tag for a second subset of data blocks. In implementations, the first and second integrity tags overlap at least one data block and are offset based on computational complexities of generating the integrity tags. A receiving endpoint generates comparison tags for each of the integrity tags and uses the comparison tags to validate an authenticity of received data. In response to validating the first and second integrity tags, data blocks covered by both the first and second integrity tags are released for use. Additional integrity tags are generated and validated for subsequent subsets of data blocks during data communication, thus reducing latency by offsetting times at which comparison tags are generated and validated.

Abstract: Parallel-split all-to-all data communication is described. An average latency between ranks among which data blocks are to be exchanged is estimated. A split factor is then derived based on the estimated rank-to-rank latency, a number of ranks involved in the all-to-all operation, as well as a size of a data block communicated between ranks. A parallel-split all-to-all system divides the ranks into a number of parallel groups defined by the split factor. Within each group, a linear all-to-all communication is performed. Once the parallel groups have completed their internal all-to-all communication, the parallel-split all-to-all system reorganizes the ranks into exchange groups using split factor. The parallel-split all-to-all system completes the all-to-all data transfer by causing ranks to exchange data blocks among one or more other ranks included in their respective exchange group.

Abstract: Processor frequency control for expected demand is described. In one or more implementations, an apparatus includes a processing system that executes instructions for satisfying a workload demand for a current window of time, and a power management circuit that controls a processor frequency of the processing system based on one or more characteristics of the workload demand for an earlier window of time. In at least one example, a system includes a memory including executable instructions of a workload, and a processor that executes the instructions for a second window of time according to a processor frequency that is controlled based on one or more characteristics of the instructions for a first window of time.

Abstract: The disclosed computer-implemented method can include reaching, by a chiplet involved in carrying out an operation for a process, a synchronization barrier. The method can additionally include receiving, by the chiplet, dedicated control messages pushed to the chiplet by other chiplets involved in carrying out the operation for the process, wherein the dedicated control messages are pushed over a control network by the other chiplets. The method can also include advancing, by the chiplet, the synchronization barrier in response to receipt of the dedicated control messages. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading data. The integrated circuit includes circuitry configured to write or read a first portion of data to or from a first memory via BIST circuitry of the first memory until a first BIST counter saturates. The integrated circuit also includes circuitry configured to write or read a second portion of the data to or from a second memory via BIST circuitry of the second memory until a second BIST counter saturates.

Abstract: Embodiments herein describe tokenizing a data sequence to perform a wildcard lookup. For example, a network device (such as a NIC or a switch) can receive a data sequence (e.g., an IP address, Uniform Resource Locator (URL), domain name, etc.) which can be broken down into separate tokens. After identifying a first token, the network device can search a wildcard lookup table to determine a first entry in the table that matches the first token. Assuming there is a match, the network device can identify an action associated with the entry. If the action is to continue with the search, the network device can then retrieve a key from the entry which it then combines with a second token in the data sequence to again search the wildcard lookup table.

Abstract: Embodiments herein describe a circuit including a user domain configured to execute user functions and a hardened domain configured to communicate with the user domain. The hardened domain includes peripheral component interconnect express (PCIe) function decoding logic having a plurality of register bits and a Trusted Execution Environment (TEE) Device Interface Security Protocol (TDISP) core communicating with the PCIe function decoding logic. The TDISP core supports a plurality of PCIe functions. Each register bit of the plurality of register bits is assigned to a respective PCIe function of the plurality of PCIe functions.

Abstract: A graphics pipeline includes a first shader that generates first wave groups, a shader processor input (SPI) that launches the first wave groups for execution by shaders, and a scan converter that generates second waves for execution on the shaders based on results of processing the first wave groups by the one or more shaders. The first wave groups are selectively throttled based on a comparison of in-flight first wave groups and second waves pending execution on the at least one second shader. A cache holds information that is written to the cache in response to the first wave groups finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first wave groups are selectively throttled by comparing how many first wave groups are in-flight and how many read requests to the cache are pending.

Abstract: In accordance with described techniques for reduction of parallel memory operation messages, a computing system or computing device includes a memory system that receives memory operation messages. A shared response component in the memory system receives responses to the memory operation messages, and identifies a set of the responses that are coalesceable. The shared response component then coalesces the set of the responses into a combined message for communication completion through a communication path in the memory system.

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit uses Cross field effect transistors (FETs) with a first device, such as n-type device, having a first channel oriented in a first direction and connected to a ground reference voltage level provided by a backside metal layer. The Cross FETs also use a second device, such as the p-type device, having a second channel oriented in a second direction orthogonal to the first direction and connected to a power supply reference voltage level provided by a frontside metal layer. A micro through silicon via (TSV) traverses the silicon substrate layer in order to be placed between the backside metal layer and the source region of an n-type device. The power connections reduce on-die area, reduces semiconductor fabrication complexity, which improves wafer yield, and reduces voltage droop, which increases performance.

Abstract: Transmitter circuitry receives a data signal and outputs a serial data signal. The transmitter circuitry includes serializer circuitry. The serializer circuitry includes data input circuitry and data serializer circuitry. The data input circuitry receives and outputs a first data signal based on a write pointer signal having a first value of values and a first clock signal. The data serializer circuitry configured to serialize the first data signal to generate a serial signal based on a read pointer signal having a second value of the values and a second clock signal. The first value differs from the second value.

Abstract: Rendering 3D geometry involves processing a very large amount of geometry. Compression techniques can be used to decrease the amount of data required for such geometry overall. A particular compression format for geometry is dense compression format, in which triangle strips are represented in highly compacted code sequences. In particular, compression code sequences describe the connectivity between triangles of a strip, thus ultimately provide a compact representation of which vertex indices comprise each triangle. A vertex index is an index into a vertex buffer that stores the actual vertex data, allowing for deduplication of such data. Though compact, such compression code sequences are somewhat tricky to decompress. A technique is provided herein for decompressing such code sequences. In particular, the technique involves a series of bitwise, arithmetic, and/or logical operations that expand out the code sequences into indices for the triangles.

Abstract: The disclosed device includes a base die and one or more stack die, and includes various components that monitor various locations on the base die and the one or more stack die. The components include sensors that provide signals including sensor data that are compared to a threshold by a controller of the base die. If the sensor data satisfies the threshold, the controller can transmit a signal to cause the base die, the one or more stack die, or a combination thereof, to perform an action, such as to throttle operations intended for the base die and one or more stack die. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Fine-grained preemption of a data flow architecture based neural processing unit (NPU) includes executing, by a controller, control-code that implements a first context in the NPU. In response to the controller detecting a preemption opcode in the control-code, detecting, by the controller, a second context awaiting execution by the neural processing unit. The second context has a priority that is greater than a priority of the first context. In response to detecting the second context, the NPU switches from executing the first context to implementing the second context.

Abstract: A power sensing circuit in a first voltage domain senses an input voltage from a second voltage domain and provides a power OK signal. The maximum supply voltage of the first voltage domain is above a maximum tolerance for devices in the first voltage domain. Accordingly, protection techniques are employed to ensure that the potential difference between any two terminals of devices in the power sensing circuit does not exceed the maximum tolerance limit. The protection techniques utilize reference voltage-based techniques including level shifting and use of protection devices in transistor stacks. An over-voltage tolerant Schmitt trigger circuit is also employed in the power sensing circuit. A trip point device on the input of the power sensing circuit utilizes a programmable bias voltage to adjust the trip point of the power sensing circuit to accommodate different maximum input voltages from the second voltage domain.

Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.