Abstract: A method and apparatus for mitigating row hammer attacks is provided. A row hammer alert is generated by a component of a memory architecture controlling operation of a memory device. The component may be a memory controller, coherency logic, or data fabric. The component obtains a physical address of an aggressor row that caused the alert and obtains an identifier of an execution context corresponding to the physical address. The component generates an error message for a processing device, the error message including the identifier of the execution context. The processing device retrieves the error message when performing a context switch. The processing device then generates an event received by the operating system. The operating system then takes action to reduce row hammer by the execution context, such as ending, restarting, or throttling the execution context.

Abstract: Selecting intermediate representation transformation for compilations is described. In accordance with the described techniques, source code is received to be compiled by a compilation system for execution by a processor of hardware. Intermediate representation transformations are selected for the source code based on system load information associated with the hardware. The intermediate representation transformations are output to the compilation system.

Abstract: A processor configured to execute one or more virtual machines (VMs) includes an input-output memory management unit (IOMMU) configured to handle memory-mapped input-output (MMIO) requests and direct memory access (DMA) requests from a processor core of the processor or one or more input/output (I/O) devices. In response to receiving an MMIO or DMA request, the IOMMU is configured to determine a VM associated with the request. The IOMMU then checks a security indicator field of an address space identifier (ASID) mask table to determine if the VM was previously the target of an attack by a malicious entity. In response to the VM previously being a target of an attack, the IOMMU denies the received MMIO or DMA request.

Abstract: Speculative cache invalidation techniques for processing-in-memory instructions are described. In one example, a system includes a cache system including a plurality of cache levels and a cache coherence controller. The cache coherence controller is configured to perform a cache directory lookup using a cache directory. The cache directory lookup is configured to indicate whether data associated with a memory address specified by a processing-in-memory request is valid in memory. The system employs speculative evaluation logic to identify whether the data associated with the processing-in-memory request is stored in the cache system before the processing-in-memory request is transmitted to the cache coherence controller. If the data is stored in the cache system, the cache system locally invalidates or flushes the data to avoid stalling the processing-in-memory request during a cache directory lookup.

Abstract: Devices, methods and systems for managing resources in a computing device. Information regarding resource usage is captured. A prediction is generated, based on the information, that resource usage by a processor will exceed a threshold during an upcoming time. An operating parameter of the processor is adjusted, based on the prediction. In some implementations, information regarding memory bandwidth is captured. A prediction is generated, based on the information, that a memory region stored in a first memory device will be addressed by a memory intensive instruction during an upcoming time period. Data stored in the memory region is moved to a second memory device, based on the prediction.

Abstract: A substrate includes a location for coupling one or more chiplets to the substrate. The location has dimensions that bound dimensions of chiplets capable of being coupled to the substrate in the location. Additionally, the location includes an interface region having connections for one or more die-to-die interfaces of the one or more chiplets and a power region that includes a power interface having connections for the one or more chiplets.

Abstract: An imaging system improves image quality, such as during a videoconference, by adjusting one or more captured images based on a model of a scene, a conference participant's face or a combination thereof. The images are adjusted in response to identification of relatively poor ambient conditions for image capture. The imaging system, such as a videoconference system, is thus able to display relatively high-quality images even in relatively poor conditions for image capture.

Abstract: A processing system includes a memory configured to store encrypted information representing state and control information for a guest virtual machine. The processing system further includes a processor configured to selectively reserve exclusive use of a set of performance monitoring counters by the guest virtual machine during execution of the guest virtual machine based on a state of a first control field accessed from the encrypted information for the guest virtual machine. The processor further is configured to permit or deny use of the set of performance monitoring counters by the guest virtual machine based on a state of a second control field set by a hypervisor and accessed from the decryption of the encrypted information for the guest virtual machine accessed from the memory.

Abstract: A system and method for characterizing the data used to train a model for machine learning inference. Training data and production data may both be fingerprinted, and the fingerprints may be compared to detect undesirable variances between training and production data. This may allow performance issues relating to differences in the training data set versus the production data set to be more easily identified. Parameters used for characterization can be determined based on the type of training data such as numerical data, image data, or audio data.

Abstract: Systems and methods for correlating performance on bare metal systems with virtualized instances such as those commonly used in cloud computing systems are disclosed. Performance data may be collected from different bare metal and cloud instances. The performance data may be used to predict the performance of an application on another system, even if the particular performance counter of interest is unavailable on the system. Using measured and estimated performance counters (e.g., instructions counters), multiple measured and unmeasured but predicted instances can be compared and sorted to assist the user in making an informed decision when selecting where to run their instance and what configuration to use.

Abstract: Disclosed devices, systems, and methods may enhance communication protocols for low latency applications. Systems may include a device and a host interconnected by a high-performance interconnect and/or communication link. The device may comprise a transmitter, a receiver, and a control unit that may manage a credit-based flow control mechanism. In some aspects, the device may initiate a push write request, send a data header with an identifier (UQID) matching the push write request identifier (CQID), and transmit the data payload. The host may receive the push write request, match the UQID with the CQID, perform the write operation, and send a completion message back to the device. The method may involve ensuring sufficient credits before initiating the push write transaction, which may help prevent data loss and ensure reliable delivery. The push write mechanism may reduce the number of link traversals required for device-to-host memory writes, potentially lowering overall latency.

Abstract: A hardware-accelerated siamese neural network device includes a first hardware-accelerated convolutional neural network (CNN) circuit configured to apply a certain weight to a first input at a specific moment of an operation. The hardware-accelerated siamese neural network device also includes a second hardware-accelerated CNN circuit configured to apply the certain weight to a second input at the specific moment of the operation. In addition, the hardware-accelerated siamese neural network device includes a classifier circuit configured to generate a score that represents a degree of similarity between the first input and the second input. Various other devices, systems, and methods are also disclosed.

Abstract: A memory controller system comprises a first memory controller for accessing a first sub-channel of a memory module, and a second memory controller for accessing a second sub-channel of the memory module. Each of the first and second memory controllers is configurable as one of a master memory controller and a slave memory controller. The master memory controller is enabled to send a global command to the memory module in response to a request, and the slave memory controller is disabled from sending the global command to the memory module in response to the request.

Abstract: Methods, devices, and systems for information routing. A destination indication corresponding to data is received. The data is transmitted on a routing path based on routing information retrieved from a routing table bypass that includes a routing cache and a match mask. In some implementations, the destination indication comprises at least a portion of a network address. Some implementations include bypassing a routing table based on the routing information being present in the routing cache or the match mask. In some implementations, a total number of entries of the routing cache is fewer than a number of addresses in a working set. In some implementations, the match mask is dynamically programmable. In some implementations, an entry of the match mask includes a bit mask, a bit match and a routing destination associated with at least a portion of an address. In some implementations, the data comprises a packet.

Abstract: A disclosed computer-implemented method may include loading a pair of input vectors of into a respective pair of registers included in a processor, each input vector associated with a different shared scale term. The method may also include storing a shared scale term corresponding to at least one of the pair of input vectors within at least one control register of the processor. The method may also include performing a vector operation that utilizes the pair of input vectors by accessing the at least one control register to retrieve the shared scale term as part of the vector operation Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A data processing system includes a memory accessing agent and a memory controller coupled to the memory accessing agent. The memory controller includes an ECC check circuit for detecting errors in a data element and extracting metadata from an error correcting code, in which the detecting and extracting includes forming a plurality of error statuses based on the data element and the error correcting code for different combinations of metadata, and picking a final status and final metadata based on the plurality of error statuses.

Abstract: Systems, methods, and non-transitory computer-readable media for dynamic voltage margin adjustment are disclosed. In some aspects, a system includes a processor, a power supply monitor (PSM) configured to measure voltage levels of the processor, and a voltage control module. The voltage control module may monitor minimum voltage levels reported by the PSM, compare the minimum voltage levels to one or more thresholds, and dynamically adjust a voltage margin applied to the processor based on the comparison. The voltage margin adjustment may be performed in real-time and may account for different workload characteristics, potentially optimizing processor performance and power efficiency.

Abstract: A method of preloading address translation information directly into cache memory of an IOMMU includes storing the address translation information in a register set of memory management input/output registers of an input-output memory management unit and loading the address translation information into cache memory of the input-output memory management unit. The address translation information includes a virtual address and a corresponding physical address of system memory of a computing system. The address translation information is sent by software being executed by a processor of the computing system. The address translation information is received directly from the processor.

Abstract: A technique for building a bounding volume hierarchy is disclosed. The technique subdividing a candidate box node based on a resolution to generate a plurality of cells of the candidate box node; identifying a plurality of nodes of a triangle set collection that fit within the cells; generating a plurality of candidate splits based on the plurality of nodes; selecting a candidate split based on a selection criterion to obtain a selected candidate split; and generating child box nodes for a box node of a bounding volume hierarchy under construction, based on the selected candidate split.

Abstract: A technique for performing ray tracing operations is provided. The technique includes for a ray being tested for intersection with geometry associated with a bounding volume hierarchy, traversing to a pre-filtering node that includes information for filtering out triangles of a leaf node of the bounding volume hierarchy; evaluating a quantized ray that corresponds to the ray against quantized triangles of the pre-filtering node to filter out one or more triangles of the leaf node from consideration; and testing the triangles of the leaf node that are not filtered out and not testing the triangles of the leaf node that are filtered out.