Abstract: Multi-stack compute chip and memory architecture is described. In accordance with the described techniques, a package includes a plurality of computing stacks, and each computing stack includes at least one compute chip and a memory. The package also includes one or more interconnects that couple the computing stacks to at least one other computing stack for sharing the memory in a coherent fashion across the plurality of computing stacks.

Abstract: A computing node in a computing cluster includes at least a key generator and an encryption engine. The key generator implements a key derivation function and generates a first data encryption key based on a key derivation key. The key derivation key is a global security association encryption key shared by a plurality of nodes in the computing cluster. The first data encryption key is unique to a node pair comprising the first node and a second node of the plurality of nodes. The encryption engine encrypts a data packet using the first data encryption key.

Abstract: An apparatus and method for efficiently processing vector memory accesses on an integrated circuit. In various implementations, a computing system includes a parallel data processing circuit with multiple, replicated compute circuits. Each compute circuit includes a cache that stores temporary data. A control circuit that identifies an instruction of the in-fight wavefronts as a long-latency vector memory access instruction with an indication specifying that a destination targets data storage in the cache, rather than a vector register file. The control circuit assigns a cache line for the vector memory access instruction while foregoing vector register assignment. The control circuit sends a data retrieval request to one or more higher levels of a cache memory subsystem. When the requested data has arrived, the control circuit stores the requested data in the assigned cache line and sends a notification to the corresponding SIMD circuit.

Abstract: To render a batch of primitives, an acceleration unit (AU) first partitions a frame to be rendered into two or more tiles. For each primitive of the batch of primitives, the AU then determines whether the primitive is at least partially visible in each tile of the frame. Based on a primitive being at least partially visible in a tile, the AU stores geometry data of the primitive in the tile in a corresponding per-tile queue allocated to the tile. For each tile and using the geometry data in the per-tile queue allocated to the tile, the AU then performs one or more depth sub-passes to generate depth pre-pass data that is stored in the per-tile queue allocated to the tile. The AU then renders the batch of primitives based on the depth pre-pass data stored in the per-tile queues.

Abstract: A chip package includes a package substrate, an integrated circuit (IC) die disposed on the package substrate, and a lid assembly disposed over the IC die. The lid assembly includes a top plate having a lower surface facing the IC die and an outer shoulder. The lid assembly also includes a retainer having a lower surface secured to the package substrate and an inner shoulder retaining to the outer shoulder. The inner shoulder is configured to limit upward movement of the top plate, and expansion of the retainer is decoupled from expansion of the top plate.

Abstract: Rather than collecting flow logs at a central location, and then processing these flow logs to create general purpose or specialized data stores, the embodiments herein rely on the network appliances to create the flow logs and metadata that indexes these flow logs. The flow logs and the metadata can then be collected at the central location (e.g., a central analyzer) and merged with flow logs and metadata generated by other network appliances to yield a data store that can be used to analyze the flow logs in computing environment (e.g., a data center).

Abstract: Systems and devices for signal redundancy in stacked chip architectures can include an integrated circuit that incorporates a voting circuit. The voting circuit can be configured to receive multiple redundant copies of a signal input and remedy faults in a transmission pathway of the signal input by producing a signal output that reflects a majority among received versions of the signal input.

Abstract: A semiconductor device includes one or more active devices disposed between a processor die and a package substrate. The semiconductor device includes a first layer with a processor die, a second layer with one or more active devices, and a third layer with a package substrate, where the second layer is disposed between the first and third layers. The one or more active devices are semiconductor-based devices, such as voltage regulators, that participate in supplying power to the processor die and are electrically connected to the processor die using various connection configurations. The implementations use short path lengths for improved performance with a compact structure that avoids the use of edge wiring or interposers without occupying processor die space. Implementations include the use of through-silicon vias (TSVs) to provide short path lengths while reducing the number of connection resources used by the one or more power components.

Abstract: The disclosed device provides ringing mitigation. The device, for example, is a working group processor including a local controller that measures the voltage level within the device and compares the voltage level to a threshold voltage level. If the controller determines that the voltage level is less than the threshold voltage level, the controller determines that a voltage-related event, such as a voltage droop, is occurring within the device. In response to detection of the voltage-related event, the controller selects and injects a stall pattern to stall workloads being processed by the device. The reduction in workloads reduces an activity counter, which thereby mitigates ringing within the device. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Capacitive sensing for device power management is described. In accordance with the described techniques, a device includes one or more capacitive sensors, and a sensor processor communicatively coupled to one or more capacitive sensors. The sensor processor receives a capacitance measurement from the one or more capacitive sensors, and controls power consumption of the device based on whether the capacitance measurement indicates that a human user is handling the device.

Abstract: Handling audio artifacts within digital audio includes extracting a plurality of audio generation features from a portion of a digital audio stream preceding a selected frame of the digital audio stream. A plurality of artifact detection features are extracted from the selected frame. An audio artifact within the selected frame is detected by processing the plurality of artifact detection features through a first machine learning model trained to detect audio artifacts. In response to detecting the audio artifact, a replacement frame is generated by processing the audio generation features through a second machine learning model trained to generate replacement frames. The selected frame including the audio artifact is replaced within the digital audio stream with the replacement frame.

Abstract: Embodiments herein describe a NIC that generates unique IDs for data flows using data fields within packets. The flow table can include multiple sub-entries that can map to the same IP ID. Each sub-entry in the flow table can be assigned a different key that serves as a unique ID for the flow for matching to packets that belong to the same network flow.

Abstract: A system and method for efficient data transfer in a computing system are described. A computing system includes multiple nodes that receive tasks to process. A bridge interconnect transfers data between two processing nodes without the aid of a system bus on the motherboard. One of the multiple bridge interconnects of the computing system is an optical bridge interconnect that transmits optical information across the optical bridge interconnect between two nodes. The receiving node uses photonic integrated circuits to translate the optical information into electrical information for processing by electrical integrated circuits. One or more nodes switch between using an optical bridge interconnect and a non-optical bridge interconnect based on one or more factors such as measured power consumption and measured data transmission error rates.

Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.

Abstract: A chip package includes a package substrate and an integrated circuit (IC) die disposed on the package substrate. The IC dies includes a security asset. The chip package also includes a glass based shield selectively disposed on the IC die and above the security asset. The glass based shield is configured to block access to the security asset. In some embodiments, the chip package includes an oxide layer disposed between the glass based shield and the IC die. In some embodiments, the chip package includes a detection module and a wire connecting the detection module to the glass based shield. The detection module is configured to generate and send a serial bit stream to the glass based shield. The detection module is also configured to monitor for changes in the serial bit stream returning from the glass based shield. Changes detected in the serial bit stream indicates the glass based shield has been tampered.

Abstract: A processing system includes a driver and an accelerated processing unit including a processor. The processor is configured to initiate a status check of wavefronts being executed by the accelerated processing unit responsive to receiving a status inquiry from the driver. Responsive to the status check indicating a hang, the processor is configured to employ a machine learning algorithm to selectively extract data from one or more registers of the accelerated processing unit. For example, in some cases, the one or more registers are local to one or more compute units of the accelerated processing unit. The processor is further configured to export the data from the accelerated processing unit prior to the accelerated processing unit being reset.

Abstract: An error sampling and decoding system is disclosed. The system includes a reference circuit configured to generate first and second reference values; a comparator configured to receive a first error symbol, and to generate serial error data representing the first error symbol based on successive comparisons of the first error symbol with the first and second reference values; and a deserializer circuit configured to generate parallel data corresponding with the first error symbol based on the serial error data.

Abstract: Systems and methods for Neural Texture Block Compression (NTBC) of graphics textures using neural networks are disclosed. NTBC employs multi-layer perceptron (MLP) networks to map uncompressed textures to block-compressed formats, such as BC1 and BC4, achieving storage reductions while maintaining reasonable visual quality. The methods and systems use MLPs to compress textures in BC1 and BC4 formats. A first neural network comprises an endpoint network that predicts endpoints for each data point of a block of a texture. The second neural network is a color network which predicts original colors of uncompressed textures. To encode the inputs to these neural networks, multi-resolution feature grids are used that allows for usage of small MLPs and encourages model optimization.

Abstract: Devices, methods, and systems for load fusion. In an explicit approach, a first load operation and a second load operation, in a stream of operations, are replaced with a single load operation. One or more operations, configured to move and shift a value stored in a destination register of the single load operation, are inserted after the single load operation in the stream of operations. In an implicit approach, Information of a first load operation is inserted into a tracking table. Information of a second load operation is inserted into the tracking table responsive to an address of the second load operation being within a range. A load operation is executed from an address indicated by the first load operation and from an address indicated by the second load operation based on the tracking table.

Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to determine, for an input tile of an image, a receptive field via backward propagation and determine a size of the input tile based on the receptive field and an amount of local memory allocated to store data for the input tile. The processor determines whether the amount of local memory allocated to store the data of the input tile and padded data for the receptive field.