Abstract: A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer to the support face and removing the support substrate from the at least one conductive layer. The at least one interconnector is adhered to the film substrate for forming an interposer. The method further involves bonding a integrated circuit chip to the at least one conductive layer of the interposer and disposing a compound over the support face to thereby encapsulate the integrated circuit chip and the least one conductive layer for forming an encapsulated package therefrom. Portions of the at least one conductive layer is then exposed by removing the film substrate from the encapsulated package.

Abstract: A semiconductor package for optical sensing and method of manufacture thereof is disclosed. The semiconductor package comprises a substrate for transmitting radiation and an integrated circuit chip for sensing the radiation. A plurality of connectors for electrical transmission is disposed on the substrate and a plurality of pillars for facilitating electrical communication between the plurality of connectors and the integrated circuit chip is disposed between at least one of the plurality of connectors and the integrated circuit chip.

Abstract: A method for joining a semiconductor integrated circuit (IC) chip in a flip chip configuration, via pillar bump, to solderable metal contact pads, leads or circuit lines on the ciruitized surface of a chip carrier, as well as the resulting chip package, are disclosed. The semiconductor device is attached to the substrate via no flow underfill under thermal compression bonding. Integration of this structure and assembly method enables to incorporate low coefficient of thermal expansion (CTE) no flow underfill and achieve high assembly yield, especially for lead free bumps. The present invention provides a solution for a flip chip package with fine pitch, high pin count and lead free requirements.

Abstract: High performance integrated circuits generally have high heat generating capabilities. During powering up of these integrated circuits under typical operating conditions, heat generation is unavoidably accelerated. When the accumulated heat is not adequately dissipated, the high temperature of the integrated circuits will lead to overheating which in turn, causes irreversible damage to the integrated circuits. Conventional thermal management methods using bumps of a ball grid array (BGA) as heat paths to a heat sink has low thermal transmissibility due to the substantially spherical shape thereof. Metallic columns formed by vias in substrates have dimensional restrictions that also limit thermal transmissibility thereof. Coupling of semiconductor device directly to a heat sink formed in a substrate will also require undesirable structural modifications to the substrate, for example a concavity formed therein, for accommodating the integrated circuit therewithin.

Abstract: A structure for high quality factor inductor operation formed on a semiconductor chip is disclosed. The structure comprises a plurality of pillars displaced from the semiconductor chip for forming an inductor. The plurality of pillar is arranged in an electrically inductive formation and at least one of the plurality of pillars is electrically coupled to the semiconductor chip, wherein each of the plurality of pillars abuts at least one and no more than two adjacent pillars and is electrically communicable with the at least one and no more than two adjacent pillars.

Abstract: As the functionality, speed and portability of consumer electronics increases, so does the need for more circuitry to be packed into smaller spaces. All this leads to the fact that the size of a device is now becoming more often a function of the circuit board or module size than anything else. In order to achieve size reduction of multi-featured products, passive components on the surface of the circuit need to be eliminated by burying them within the inner layers of the printed wiring board. Embedded passives are passive components placed between the interconnecting substrates of a printed wiring board. Implementation of embedded passives reduces space requirements and enables more silicon devices to be placed on the same sized substrate, thereby allowing functional potential of small electronic devices to increase. However, additional steps are conventionally required for embedding passive components within the interconnect layer between substrates.

Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.

Abstract: Wireless devices use protruding antennas for transmitting and receiving data signals. These protruding antennas govern the size and dimensions of these wireless devices. Perpetual reduction in the size of these wireless devices has resulted in an increasing need and desire to eliminate the protruding antennas. Solutions such as reducing the protruding antenna to a stub or using retractable antennas have limitations. The antenna stub sacrifices performance for size reduction. Additionally, the retractable antennas are usually physically separated from the integrated circuit. Electrical connectors interconnecting the external antenna and the integrated circuit can mechanically fail due to connector flexure.

Abstract: A method for fabricating a chip scale package is described. The method utilizes wafer level processes to obtain a chip level package. The method particularly avoids the use of mechanical grinding by the novel use of molding, extruding, and etching technology.

Abstract: A layer of gold (405) is disposed on upper surfaces (225) of copper pillars (210) on a bumped wafer (205). Coating material (410) is then applied to a level which is less than the height of the copper pillars (210), and etchant is disposed to remove coating material on the layer of gold (405) and to remove coating material (410) adhering to side surfaces of the copper pillars (210). Solder deposits are then disposed on the gold layer and reflowed to form balls (405) on the ends of the copper pillars (210), with the copper pillars (210) protruding into the solder balls (405).

Abstract: A method of assembling a package having an exposed die comprising the following steps. A die attached to a substrate by connectors is provided. The die having a backside. Encapsulate is formed around the die and over the backside of the die to form an encapsulated package. The encapsulate overlying the backside of the die and a portion of the backside of the die are removed using a backside exposure process to complete the assembled package having the die exposed.

Abstract: A semiconductor chip packaging structure is described. The structure comprising of a semiconductor chip interconnected to a recessed lead frame and the resultant assembly encapsulated in a molding compound. The final product is a reverse mounted semiconductor chip in a leadless quad flat pack configuration. A second embodiment allows for the semiconductor chip backside to be exposed for thermal enhancements. Manufacturing methods are also described for the two embodiments disclosed.

Abstract: A method for fabricating a chip scale package is described. The method utilizes wafer level processes to obtain a chip level package. The method particularly avoids the use of mechanical grinding by the novel use of molding, extruding, and etching technology.

Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is.

Abstract: A method for joining a semiconductor integrated circuit (IC) chip in a flip chip configuration, via pillar bump, to solderable metal contact pads, leads or circuit lines on the ciruitized surface of a chip carrier, as well as the resulting chip package, are disclosed. The semiconductor device is attached to the substrate via no flow underfill under thermal compression bonding. Integration of this structure and assembly method enables to incorporate low coefficient of thermal expansion (CTE) no flow underfill and achieve high assembly yield, especially for lead free bumps. The present invention provides a solution for a flip chip package with fine pitch, high pin count and lead free requirements.

Abstract: A method and structure for controlling solder spread in a predefined/designed area during flip chip assembly build is disclosed. Using conventional processes used in the art blind holes or dimples are incorporated onto the lead frame which then act as containers or wells trapping the solder and thereby preventing it from spreading wider.

Abstract: A method of assembling a package having an exposed die comprising the following steps. A die attached to a substrate by connectors is provided. The die having a backside. Encapsulate is formed around the die and over the backside of the die to form an encapsulated package. The encapsulate overlying the backside of the die and a portion of the backside of the die are removed using a backside exposure process to complete the assembled package having the die exposed.

Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.

Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is.

Abstract: A method of forming an underfilled semiconductor package comprises the steps of: providing a substrate (300) with raised terminal portions (305), disposing underfill compound (5) with filler (27) on the substrate (300), placing a bumped semiconductor die (40) on the substrate (300) with bumps (45) abutting upper surfaces (310) of the raised terminal portions (305), and reflowing the assembly. During the reflow process, the raised terminal portions (305) and the bumps (45) melt and displace the filler (27) in the underfill compound (5) away from between the bumps (45) and the raised terminal portions (305). This prevents the filler (27) from forming a barrier. The molten solder forms interconnects between the pads (46) and the raised terminal portions (305).