Patents Assigned to Advanpack Solutions PTE, Ltd.
  • Package design and method of manufacture for chip grid array
    Patent number: 6929981
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: August 16, 2005
    Assignee: Advanpack Solutions PTE, Ltd.
    Inventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano