Patents Assigned to Advanpack Solutions PTE, Ltd.
  • Patent number: 10446457
    Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: October 15, 2019
    Assignee: Advanpack Solutions Pte Ltd
    Inventors: Shoa Siong Lim, Hwee Seng Chew
  • Publication number: 20190035643
    Abstract: A semiconductor structure for manufacturing a semiconductor package device is provided. The semiconductor structure includes a carrier and a dielectric layer. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer. The dielectric layer is formed on the first surface of the carrier. The carrier supports the dielectric layer.
    Type: Application
    Filed: September 19, 2018
    Publication date: January 31, 2019
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Jimmy Hwee-Seng CHEW, Kian-Hock LIM, Oviso Dominador Fortaleza, JR., Shoa-Siong LIM
  • Patent number: 10154588
    Abstract: A manufacturing method of a semiconductor package includes the following steps. Firstly, a conductive carrier is provided. Then, a first conductive layer is formed on a lower surface of the conductive carrier. Then, a second conductive layer is formed on a lower surface of the first conductive layer, wherein the second conductive layer and the first conductive layer together constitute a conductive structure. Then, an electrical component is disposed on the lower surface of the first conductive layer. Then, a first package body encapsulating the first conductive layer, the second conductive layer and the electrical component but not covering an edge of the lower surface of the conductive carrier is formed. Then, a portion of the first package body is removed. Then, partial material of the conductive carrier is removed, such that a reserved part of the conductive carrier forms a ring-shaped conductive structure.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: December 11, 2018
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Raymond Lim
  • Patent number: 10109503
    Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a carrier. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: October 23, 2018
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Jimmy Hwee-Seng Chew, Oviso Dominador Jr Fortaleza, Kian-Hock Lim, Shoa-Siong Lim
  • Patent number: 10049950
    Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: August 14, 2018
    Assignee: Advanpack Solutions Pte Ltd
    Inventors: Shoa Siong Lim, Hwee Seng Chew
  • Patent number: 9892916
    Abstract: A manufacturing method of a package substrate is provided. A conductive substrate is provided. A first photoresist layer is patterned to form first openings. A first conductive layer is formed in the first openings. A second photoresist layer is patterned to form second openings. A second conductive layer contacting the first conductive layer is formed in the second openings. The first and second photoresist layers are removed. A dielectric layer covers the first, second conductive layers and a portion of the conductive substrate. A portion of the dielectric layer is removed. A third photoresist layer is patterned to form a third opening. A portion of the conductive substrate is removed to form a fourth opening. The third photoresist layer is removed. A fourth photoresist layer is patterned to form a fifth opening. A bonding pad is formed in the fifth opening. The fourth photoresist layer is removed.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: February 13, 2018
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Shoa-Siong Raymond Lim, Hwee-Seng Jimmy Chew
  • Patent number: 9847268
    Abstract: A semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package includes a device carrier and a stiffener structure. The device carrier includes at least one insulating layer and at least conductive layer defining at least one trace layout unit. The stiffener structure is disposed on the device carrier, surrounding the periphery of the at least one trace layout unit. The stiffener structure is disposed away from the periphery of the at least one trace layout unit, forming a cavity with the device carrier. The shape and disposition of the stiffener structure enhance the strength of the semiconductor package, impeding flexure to the semiconductor package.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: December 19, 2017
    Assignee: ADVANPACK SOLUTIONS PTE. LTD.
    Inventors: Shoa Siong Lim, Kian Hock Lim
  • Publication number: 20170303399
    Abstract: A manufacturing method of a semiconductor package includes the following steps. Firstly, a conductive carrier is provided. Then, a first conductive layer is formed on a lower surface of the conductive carrier. Then, a second conductive layer is formed on a lower surface of the first conductive layer, wherein the second conductive layer and the first conductive layer together constitute a conductive structure. Then, an electrical component is disposed on the lower surface of the first conductive layer. Then, a first package body encapsulating the first conductive layer, the second conductive layer and the electrical component but not covering an edge of the lower surface of the conductive carrier is formed. Then, a portion of the first package body is removed. Then, partial material of the conductive carrier is removed, such that a reserved part of the conductive carrier forms a ring-shaped conductive structure.
    Type: Application
    Filed: June 29, 2017
    Publication date: October 19, 2017
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy CHEW, Shoa-Siong Raymond LIM
  • Patent number: 9754899
    Abstract: A semiconductor structure and a method of fabricating the same. The semiconductor structure comprises: a layer element, one or more supporting elements disposed on a first surface of the layer element, and one or more anchoring elements disposed within the layer element and connected to the one or more supporting elements to couple the one or more supporting elements to the layer element to strengthen the layer element.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: September 5, 2017
    Assignee: Advanpack Solutions PTE LTD
    Inventors: Shoa Siong Raymond Lim, Hwee Seng Jimmy Chew
  • Patent number: 9723717
    Abstract: A substrate structure, a semiconductor package and a manufacturing method of semiconductor package are provided. The substrate structure comprises a conductive structure, an electrical component, a package body and a ring-shaped conductive structure. The conductive structure comprises a first conductive layer and a second conductive layer. The first conductive layer has a lower surface. The second conductive layer and the electrical component are formed on the lower surface of the first conductive layer. The package body encapsulates the conductive structure and the electrical component and has an upper surface. The ring-shaped conductive structure surrounds the conductive structure and the electrical component and is disposed at the edge of the upper surface of the package body to expose the conductive structure.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: August 1, 2017
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Raymond Lim
  • Patent number: 9653323
    Abstract: A manufacturing method of a substrate structure is provided. The method includes the following steps. Firstly, a conductive carrier is provided. Then, a first metal layer is formed on the conductive carrier. Then, a second metal layer is formed on the first metal layer. Then, a third metal layer is formed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer, and the first metal layer, the second metal layer and the third metal layer form a conductive structure.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: May 16, 2017
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy Chew, Shoa-Siong Raymond Lim
  • Patent number: 9583449
    Abstract: A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor device. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The traces are disposed in the dielectric layer and are exposed on the second dielectric surface. The electrical pads are disposed on the first dielectric surface. The studs are disposed in the dielectric layer and are exposed on the first dielectric surface. The studs are electrically connected to the traces and the electrical pads. The semiconductor device is disposed on the second dielectric surface and electrically connected to the traces.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: February 28, 2017
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy Chew, Kian-Hock Lim, Oviso Dominador Fortaleza, Jr., Shoa-Siong Raymond Lim
  • Publication number: 20160329306
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.
    Type: Application
    Filed: July 18, 2016
    Publication date: November 10, 2016
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy CHEW, Chee-Kian ONG, Bin Chichik ABD. RAZAK
  • Publication number: 20160293416
    Abstract: A manufacturing method of a package substrate is provided. A conductive substrate is provided. A first photoresist layer is patterned to form first openings. A first conductive layer is formed in the first openings. A second photoresist layer is patterned to form second openings. A second conductive layer contacting the first conductive layer is formed in the second openings. The first and second photoresist layers are removed. A dielectric layer covers the first, second conductive layers and a portion of the conductive substrate. A portion of the dielectric layer is removed. A third photoresist layer is patterned to form a third opening. A portion of the conductive substrate is removed to form a fourth opening. The third photoresist layer is removed. A fourth photoresist layer is patterned to form a fifth opening. A bonding pad is formed in the fifth opening. The fourth photoresist layer is removed.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 6, 2016
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Shoa-Siong Raymond LIM, Hwee-Seng Jimmy CHEW
  • Publication number: 20160268225
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.
    Type: Application
    Filed: May 18, 2016
    Publication date: September 15, 2016
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy CHEW, Chee-Kian ONG
  • Patent number: 9396982
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: July 19, 2016
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong, Bin Chichik Abd. Razak
  • Publication number: 20160189981
    Abstract: A manufacturing method of a substrate structure is provided. The method includes the following steps. Firstly, a conductive carrier is provided. Then, a first metal layer is formed on the conductive carrier. Then, a second metal layer is formed on the first metal layer. Then, a third metal layer is formed on the second metal layer, wherein each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface, the first surface of the third metal layer is connected to the second surface of the second metal layer, the surface area of the first surface of the third metal layer is larger than the surface area of the second surface of the second metal layer, and the first metal layer, the second metal layer and the third metal layer form a conductive structure.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 30, 2016
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy CHEW, Shoa-Siong Raymond LIM
  • Patent number: 9379044
    Abstract: A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer.
    Type: Grant
    Filed: October 20, 2012
    Date of Patent: June 28, 2016
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Shoa-Siong Raymond Lim, Hwee-Seng Jimmy Chew
  • Patent number: 9362206
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: June 7, 2016
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy Chew, Chee-Kian Ong
  • Publication number: 20160118349
    Abstract: A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor device. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The traces are disposed in the dielectric layer and are exposed on the second dielectric surface. The electrical pads are disposed on the first dielectric surface. The studs are disposed in the dielectric layer and are exposed on the first dielectric surface. The studs are electrically connected to the traces and the electrical pads. The semiconductor device is disposed on the second dielectric surface and electrically connected to the traces.
    Type: Application
    Filed: December 7, 2015
    Publication date: April 28, 2016
    Applicant: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy CHEW, Kian-Hock LIM, Oviso Dominador Jr FORTALEZA, Shoa-Siong Raymond LIM