Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: An amplitude-stabilized second-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a replica cell having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a control circuit coupled to the differential output of the replica cell and driving the load control inputs of the main cell and the replica cell. The main cell and the replica cell are multiplier cells each having a variable load. The control circuit includes a first amplifier for generating a single-ended peak signal and a second amplifier for generating the load control voltage from the difference between the replica cell single-ended peak output signal and a single-ended peak reference signal.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: Circuits and a corresponding method are used to eliminate or greatly reduce SET induced glitch propagation in a radiation hardened integrated circuit. A clock distribution circuit and an integrated circuit portioning can be radiation hardened using one or two latch circuits interspersed through the integrated circuit, each having two or four latch stages.

Abstract: A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A flexible semiconductor package is formed by interposing a flexible substrate between a tungsten stiffener and a die. A tungsten stiffener is bonded to a first surface of the flexible substrate prior to flip chip bonding or die attach of a die to a second surface of the flexible substrate. The tungsten stiffener is dimensioned so as to substantially overlap the die and provide a rigid and flat surface on which the die/flexible substrate bonding occurs. The flat and rigid characteristic of a tungsten stiffener optimizes the electrical and mechanical bond between the die and the flexible substrate as well as minimizing CTE mismatch.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected.

Abstract: A flexible semiconductor package is formed by interposing a flexible substrate between a tungsten stiffener and a die. A tungsten stiffener is bonded to a first surface of the flexible substrate prior to flip chip bonding or die attach of a die to a second surface of the flexible substrate. The tungsten stiffener is dimensioned so as to substantially overlap the die and provide a rigid and flat surface on which the die/flexible substrate bonding occurs. The flat and rigid characteristic of a tungsten stiffener optimizes the electrical and mechanical bond between the die and the flexible substrate as well as minimizing CTE mismatch.

Abstract: A regulator circuit includes a voltage regulator having a stability control input and an output for providing a regulated output voltage, an amplifier circuit having an input for receiving an error voltage of the voltage regulator, and an output, and a control circuit having an input coupled to the output of the amplifier and an output coupled to the stability control input of the voltage regulator, such that the regulator stability is maximized while the error voltage is minimized. The voltage regulator includes an LDO voltage regulator, the amplifier circuit includes an operational amplifier circuit, and the control circuit includes a load-sensing or load-replicating circuit.

Abstract: An amplitude-stabilized third-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a plurality of replica cells having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a plurality of control circuits coupled to the differential outputs of the replica cells, and driving the load control inputs of the replica cells and the weighted inputs of a signal combiner driving the load control input of the main cell. The main cell and the replica cells each include a cross-coupled differential cell having a variable load.