Abstract: An amplitude-stabilized second-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a replica cell having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a control circuit coupled to the differential output of the replica cell and driving the load control inputs of the main cell and the replica cell. The main cell and the replica cell are multiplier cells each having a variable load. The control circuit includes a first amplifier for generating a single-ended peak signal and a second amplifier for generating the load control voltage from the difference between the replica cell single-ended peak output signal and a single-ended peak reference signal.

Abstract: A capacitance compensation circuit includes a plurality of switches having a first node coupled to an input terminal, a plurality of capacitors each coupled to a respective second node of the plurality of switches, and an adjustment circuit for providing a plurality of adjustable bias levels to a plurality of switch control nodes to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A capacitance compensation circuit includes an input terminal, a plurality of switches coupled to the input terminal, a plurality of varactors coupled to the plurality of switches, and a plurality of blocking capacitors coupled between the plurality of switches and the plurality of varactors. The capacitance compensation circuit further includes a plurality of adjustable biasing circuits to precisely compensate for linear and parabolic voltage dependent components of an input or other capacitor. Two such circuits can be used with a single input terminal to compensate for both increasing and decreasing voltage dependent characteristics of a target capacitor.

Abstract: A radiation-hardened reference circuit includes a precision voltage reference circuit for generating a current-controlling voltage at first and second terminals, a driver circuit for receiving the current-controlling voltage at first and second terminals and for generating an output reference voltage, and a differential sampling circuit having first and second input terminals coupled to the first and second terminals of the voltage reference circuit, and first and second output terminals coupled to the first and second terminals of the driver circuit.

Abstract: A simple voltage detection circuit has few circuit elements, but provides a voltage output that is substantially temperature insensitive. The voltage detection circuit includes a diode-connected transistor, a cascode-connected transistor, as well as first and second resistors coupled between ground and a ramped power supply voltage. The diode-connected transistor exhibits a negative temperature coefficient. The on resistance of the cascode-connected transistor increases with temperature and thus the voltage dropped across the cascode-connected transistor also increases with temperature. By correctly sizing the cascode-connected device, the negative and positive temperature coefficients of the diode-connected and cascode-connected devices can be substantially cancelled out.

Abstract: A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.

Abstract: A delay line appropriate for use in a POR circuit or other integrated circuit in a space environment combines three separate circuit techniques to improve performance without unnecessarily increasing circuit area or adding to manufacturing costs when compared to a simple inverter delay line. The delay line of the present invention uses the selective placement of capacitors throughout the delay line, one-sided current starving, and the incorporation of one-sided Schmitt trigger circuits. Performance of the delay line is substantially immune to SEGR events (“Single Event Gate Rupture”) and SET events (“Single Event Transients”). Spurious signals produced by SEGR and SET events are quickly and substantially attenuated.

Abstract: An autodetect circuit for a router system includes an interface to two bidirectional serial links, an input multiplexer circuit coupled to one side of the link interface for receiving input data signals and clock signals, a receiver coupled to the input multiplexer circuit and to a receive FIFO, a state machine coupled to the receiver, a transmitter coupled to the state machine, a transmit FIFO, and to the other side of the link interface for transmitting output data, and a counter coupled to the state machine for controlling the input multiplexer circuit. The autodetect circuit determines which of the two links “A” or “B” is active and available for transmission. The counter is incremented whenever a link reset occurs. When the count reaches a predetermined maximum count value, a port enable signal is toggled from the default “A” link to the “B” link. When one port is enabled, any activity on the other port is ignored.

Abstract: A high speed voltage translator circuit includes a voltage divider coupled between first and second power supplies, a transconductance amplifier coupled between third and fourth power supplies including a non-inverting voltage input coupled to the voltage divider, an inverting voltage input for receiving an input signal, and a current output, and a current comparator coupled between the third and fourth power supplies having an input coupled to the current output of the transconductance amplifier, and an output for providing a translated output voltage. The translated output voltage transitions between the third and fourth power supply voltage levels, the third power supply voltage level being more positive than a first power supply voltage level, and the fourth power supply voltage level being more negative than a second power supply voltage level.

Abstract: An x-ray detector capable of directly converting x-ray radiation into electrical signals utilizes the radiation induced conductivity of various solid, electrically insulating materials. The detector is configured comprising one or more anodes and cathodes separated by various thicknesses of dielectric material wherein ionization occurs primarily in the electrodes of such detector structure. The radiation induced conductivity of the dielectric material can be modulated by controlling the size, orientation and composition of the electrodes and the dielectric materials as well as the electrical bias between anode and cathode.

Abstract: A current comparator includes an input node for receiving an input current, an output node, a first wide swing current mirror having an input coupled to the input node of the current comparator, a power node for receiving a first power supply voltage such as ground, and an output coupled to the output node of the current comparator, and a second wide swing current mirror having an input coupled to the input node of the current comparator, a power node for receiving a second power supply voltage such as VDD, and an output coupled to the output node of the current comparator. The output node can provide either a voltage or current output signal.

Abstract: A front side illuminated photo detector array is shielded from X-ray cross-talk by filling the septa between individual photo detector diodes with a high atomic number material such as tungsten. The processing circuitry is also shielded from stray X-rays by a barrier such as tungsten placed between each photo detector diode and the processing circuitry. This barrier serves a dual role as shielding the processing circuitry from stray X-ray radiation and acting as the electrical contact between the detector diode and the circuitry.

Abstract: A total ionizing dose suppression architecture for a transistor and a transistor circuit uses an “end cap” metal structure that is connected to the lowest potential voltage to overcome the tendency of negative charge buildup during exposure to ionizing radiation. The suppression architecture uses the field established by coupling the metal structure to the lowest potential voltage to steer the charge away from the critical field (inter-device) and keeps non-local charge from migrating to the “birds-beak” region of the transistor, preventing further charge buildup. The “end cap” structure seals off the “birds-beak” region and isolates the critical area. The critical area charge is source starved of an outside charge. Outside charge migrating close to the induced field is repelled away from the critical region. The architecture is further extended to suppress leakage current between adjacent wells biased to differential potentials.

Abstract: A photodiode detector array is bonded to a first surface of a first substrate and electrically coupled to the second surface of the first substrate. A shield, opaque to X-ray radiation is attached to the second surface of the first substrate. A processing chip is flip chip bonded and electrically coupled to the first surface of the second substrate. A portion of the first surface of the second substrate is physically and electrically joined to a portion of the second surface of the first substrate so as to allow processing of electrical signals from the photodiode array. The shield associated with the first substrate is aligned so as to prevent X-ray radiation from reaching the processing chip associated with second substrate. The shield and the processing chip are separated by an air space providing thermal and electrical isolation.

Abstract: An x-ray detector capable of directly converting x-ray radiation into electrical signals utilizes the radiation induced conductivity of various solid, electrically insulating materials. The detector is configured comprising one or more anodes and cathodes separated by various thicknesses of dielectric material wherein ionization occurs primarily in the electrodes of such detector structure. The radiation induced conductivity of the dielectric material can be modulated by controlling the size, orientation and composition of the electrodes and the dielectric materials as well as the electrical bias between anode and cathode.

Abstract: A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitry can be a controlled pass-gate circuit and a data latch, an adjustable threshold comparator, or two controlled latches. Transient pulse suppression is achieved with less circuitry and expense than is found in TMR circuits.

Abstract: A Data Throttling method duplicates the full-speed transmission of data so that it appears to be transmitting at a 10 Mhz rate. Additional storage elements and multiplexers are added along the data path but this completely eliminates undesirable complexity in the clock tree. In a two-bit application, data is received and transmitted two bits at a time, and yet the output 10 Mhz data rate is maintained. For an even ratio between the system clock rate and the 10 Mhz clock signal rate, bit0 is transmitted for half the time and bit1 is transmitted for the other half of the time. But if the full-speed clock rate is an odd multiple of 10 Mhz, then there will be a “split cycle” including one bit0 and one bit1.

Abstract: A photodiode detector array is bonded to a first surface of a first substrate and electrically coupled to the second surface of the first substrate. A shield, opaque to X-ray radiation is attached to the second surface of the first substrate. A processing chip is flip chip bonded and electrically coupled to the first surface of the second substrate. A portion of the first surface of the second substrate is physically and electrically joined to a portion of the second surface of the first substrate so as to allow processing of electrical signals from the photodiode array. The shield associated with the first substrate is aligned so as to prevent X-ray radiation from reaching the processing chip associated with second substrate. The shield and the processing chip are separated by an air space providing thermal and electrical isolation.

Abstract: A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.

Abstract: An autodetect circuit for a router system includes an interface to two bidirectional serial links, an input multiplexer circuit coupled to one side of the link interface for receiving input data signals and clock signals, a receiver coupled to the input multiplexer circuit and to a receive FIFO, a state machine coupled to the receiver, a transmitter coupled to the state machine, a transmit FIFO, and to the other side of the link interface for transmitting output data, and a counter coupled to the state machine for controlling the input multiplexer circuit. The autodetect circuit determines which of the two links “A” or “B” is active and available for transmission. The counter is incremented whenever a link reset occurs. When the count reaches a predetermined maximum count value, a port enable signal is toggled from the default “A” link to the “B” link. When one port is enabled, any activity on the other port is ignored.