Abstract: The disclosure provides a wireless device for use in a wireless network, systems and methods for identifying radar signals and for giving the wireless network a radar-avoidance capability. In one embodiment, the wireless device includes: (1) a pulse analyzer configured to make a determination whether a received pulse is a radar pulse and not a wireless network pulse and (2) a pulse reporter coupled to the pulse analyzer and configured to generate, if the determination is positive, a report thereof for transmission over the wireless network to a central aggregation node thereof.

Abstract: An IO interface circuit for use in a high voltage tolerant application is provided. The IO interface circuit includes a signal pad and at least a first parasitic bipolar transistor having an emitter adapted for connection to a voltage return of the interface circuit, a base adapted to receive a first control signal, and a collector connected directly to the signal pad in an open collector configuration. The interface circuit further includes a MOS control circuit coupled to the parasitic bipolar transistor and being operative to generate the first control signal. The IO interface circuit may further include an active pull-up circuit connected between a voltage supply of the interface circuit and the signal pad.

Abstract: One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.

Abstract: In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level of at least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter.

Abstract: Various data acquisition, storage and/or distribution systems and devices are described herein. As one example, a mobile data acquisition and distribution device is described. The device includes a non-volatile storage medium, a wireless interface, and a processor. The non-volatile storage medium includes instructions executable by the processor to: receive a user data set, and to store the user data set to the non-volatile storage medium. The instructions are further executable by the processor to receive a request initiated through a remote user interface via the wireless interface. Where the request is to provide the user data set to a recipient device, the instructions are further executable by the processor to provide the user data set to the recipient device via the wireless interface.

Abstract: Various systems and methods for power management are disclosed herein. For example, a modular, adaptive power management system for use in a hard disk drive system is disclosed. This modular, adaptive power management system includes a hard disk drive controller, a read channel module, a host interface controller and a power manager system. The hard disk controller includes a processor executing firmware, and the host interface controller provides for host access via a host interface. The host interface may be, for example, an ATA interface, a SATA interface, and/or other emerging serial interfaces such as MMC, CE-ATA or SDIO. The power manager system includes a power island register and an oscillation control register. Both the power island register and the oscillation control register are each at least indirectly writable via the firmware and via the host interface.

Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.

Abstract: In one embodiment, a method for writing data to a storage-device array (i) including three or more storage devices and (ii) having a plurality of stripes, each stripe having two or more sector levels, each sector level containing one sector on each storage device in the array at corresponding addresses across the storage devices. The method includes: (a) calculating a parity index based on (i) an index value for a current stripe and (ii) the number of storage devices in the array, the parity index identifying a first storage device for parity data for the current stripe; and (b) at each sector level of the current stripe: (b1) writing parity data to the first storage device identified by the parity index; and (b2) writing information to the remaining storage devices.

Abstract: A short range radio transmitter device includes a radio signal modulator and transmitter, a receiver and a controller coupled to the receiver. The controller and receiver operate to examine a frequency spectrum to select a transmission frequency for the radio signal modulator and transmitter. A receiver system for use with the transmitter includes a data channel service enabled receiver and a controller. The controller of the receiver system automatically tunes the data channel service enabled receiver to a frequency identified in a data channel service component of a received signal.

Abstract: In one embodiment, a method for demodulating and searching for a preamble signal containing a complex phasor signal is disclosed. The complex phasor is demodulated using a phasor-rotated fast transformer. A received signal is correlated with a spreading code to produce a correlated signal. The correlated signal is coherently accumulated to produce a coherently accumulated signal. A first phasor-rotated signal transformation is performed on a real component of the coherently accumulated signal, and a second phasor-rotated signal transformation is performed on an imaginary component of the coherently accumulated signal. Finally, the signal power of the transformed real and imaginary components of the coherently accumulated signal is determined.

Abstract: Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.

Abstract: An improved speakerphone for a cellular telephone, portable telephone handset, or the like. In one embodiment, a receiver provides an audio signal, and a first phase-shifter phase-shifts the audio signal by a first phase-shift amount. A second phase-shifter phase-shifts the audio signal by a second phase-shift amount and drives a loudspeaker. A processor sets the first phase-shift amount to each one of a plurality of phase-shift amounts and determines a corresponding average-to-peak ratio value of the first phase-shifted audio signal. The processor then selects one of the plurality of phase-shift amounts having a corresponding average-to-peak ratio value that meets at least one criteria (e.g., the largest one of the average-to-peak ratio values), and then sets the second phase-shift amount to be the same as the selected phase-shift amount. This enhances the perceived loudness of sound from loudspeaker.

Abstract: Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods.

Abstract: In one embodiment, a mobile station including a chassis having a display, a power reducer, a proximity sensor, and a microprocessor. The power reducer controls power consumption of the display. The proximity sensor is coupled to the chassis and causes the power consumption to be reduced when the display is within a predetermined range of an external object. The microprocessor is coupled to the proximity sensor and to the display and automatically activates the proximity sensor based on the mobile station receiving an incoming wireless telephone call.

Abstract: In one embodiment, a demodulator demodulates a multi-carrier modulated signal having two pilot tones. The demodulator calculates a first phase angle for the first pilot tone and a second phase angle for the second pilot tone based on the time-domain multi-carrier modulated signal. A timing-frequency offset estimate is calculated using the first and second phase angles. Further, a fine carrier-frequency offset estimate is calculated for each pilot tone based on the corresponding phase angle and the timing-frequency offset estimate. Each fine carrier-frequency offset estimate is combined with a coarse estimate and weighted. The weighted estimates are then combined. In further embodiments, the timing-frequency offset estimate is weighted and combined with a weighted timing-frequency offset estimate generated using a cyclic prefix. In yet further embodiments, the weighted carrier-frequency offset estimates are combined with a weighted carrier-frequency offset estimate generated using a cyclic prefix.

Abstract: Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoding method is provided that assembles M-T data packets; appends a sequence number and a payload integrity check to each of the M-T data packets; and creates T protection packets having the sequence number and payload integrity check, wherein a payload for each of the T protection packets are formed from corresponding symbols in the M-T data packets. An error correction decoding method is also provided that receives a plurality of error-free packets and one or more packets having an error; and reconstructs the one or more packets having an error by applying block erasure decoding to said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode the received packets.

Abstract: A reversible fastener is provided for a resealable bag-type container (100) having first and second opposing wall panels (102,104), each of the first and second opposing wall panels having an interior face and an exterior face. The fastener includes first and second closure mechanisms. The first closure mechanism (114) includes first and second complementary interlockable components (116,118) disposed on the interior face of each of the first and second opposing wall panels proximate a top periphery (112) of the first and second opposing wall panels. The second closure mechanism (120) includes first and second complementary interlockable components (122,124) disposed on the exterior face of each of the first and second opposing wall panels proximate a top periphery of the first and second opposing wall panels.

Abstract: A cordless telephone which allows a user to play MP3 digital audio bit stream music, using the remote handset of a cordless telephone to control the functions of the MP3 player. The cordless telephone remains usable as a typical cordless telephone with all the features and conveniences of a cordless telephone including, but not limited to, connection of a telephone call between a calling party and a called party, caller ID information, voice messaging features, etc. MP3 digital audio bit stream music may be downloaded from a remote source through, e.g., the Internet and a PC.

Abstract: A method and apparatus are disclosed for locking the most recently accessed frames in a cache memory. The most recently accessed frames in a cache memory are likely to be accessed by a task again in the near future. The most recently used frames may be locked at the beginning of a task switch or interrupt to improve the performance of the cache. The list of most recently used frames is updated as a task executes and may be embodied, for example, as a list of frames addresses or a flag associated with each frame. The list of most recently used frames may be separately maintained for each task if multiple tasks may interrupt each other. An adaptive frame unlocking mechanism is also disclosed that automatically unlocks frames that may cause a significant performance degradation for a task. The adaptive frame unlocking mechanism monitors a number of times a task experiences a frame miss and unlocks a given frame if the number of frame misses exceeds a predefined threshold.

Abstract: An automatic gain control (AGC) for use in a digital radio receiver that allows at least two types of input signal to be processed using a single receiver front end by supporting two modes of operation, each optimized for one particular signal type, and a third mode not optimized for either. The AGC enables smooth switching between the optimized modes of operation via the non-optimized mode. By measuring a difference in the strength between the demodulated signals, and comparing that to two preset values, the AGC controls which mode of operation to place the receiver in. Modes of operation are maintained by adjusting the gain of a variable gain amplifier (VGA), so that an appropriate incoming signal is amplified to a level that is suitable for an analogue-to-digital (ADC) converter. The AGC is compatible with existing satellite digital audio radio system (SDARS) transmission capabilities.