Abstract: An apparatus including automatic gain control (AGC) includes at least one variable gain amplifier (VGA) operative to receive an input signal and to generate an amplified signal. A gain of the VGA is controlled as a function of at least a first control signal. The apparatus further includes an AGC circuit coupled to the VGA and being operative to generate the first control signal. The AGC circuit has a bandwidth that is controlled as a function of at least the amplified signal and a second control signal, the second control signal being indicative of a motion of the apparatus.

Abstract: Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.

Abstract: A method and apparatus are disclosed for canceling cross-talk in a frequency-division multiplexed communication system. The disclosed frequency-division multiplexed communication system employs multiple carriers having overlapping channels and provides an improved cross-talk cancellation mechanism to address the resulting interference. Bandwidth compression is achieved using n level amplitude modulation in each frequency band. An FDM receiver is also disclosed that decomposes the received broadband signal into each of its respective frequency bands and returns the signal to baseband in the analog domain. Analog requirements are relaxed by removing cross-talk from adjacent RF channels, from image bands, and minimizing the performance degradation caused by In-phase and Quadrature-phase (I/Q) phase and gain mismatches in modulators and demodulators. The disclosed transmitter or receiver (or both) can be fabricated on a single integrated circuit.

Abstract: Various embodiments of the present invention provide systems and methods for branch prediction. As an example, some embodiments of the present invention provides processor circuits that include a program address circuit, a branch target buffer, a branch prediction replacement circuit, and an execution pipeline. The branch target buffer includes a plurality of entries each associated with a respective change of flow instruction. Each entry includes an indication of an entry source and a next program address corresponding to the respective change of flow instruction. The branch prediction replacement circuit is operable to determine replacement priorities of the plurality of entries based at least in part on the entry source for each of the plurality of entries. The execution pipeline receives an executable instruction corresponding to one of the next program addresses.

Abstract: A method of processing cells in a communication system includes obtaining a cell, causing it to be stored, determined if it is associated with a loss event, and if so, causing it to be tagged with a lost cell indicator. An apparatus for processing cells includes a cell processing module and a cell buffer interface that can interface with a cell buffer. The processing module is configured to obtain a cell, cause it to be stored through the buffer interface, determine if it is associated with a loss event, and if so, cause it to be tagged with a lost cell indicator. The lost cell indicator can preferably be a compressed lost cell indicator. The inventive tagging enhances computational efficiency compared to approaches that require moving a stored cell to make room for a complete dummy cell.

Abstract: A memory circuit includes an operational memory and a monitor circuit comprising a circuit element in the operational memory and/or a circuit element substantially identical to a corresponding circuit element in the operational memory. The monitor circuit is operative to measure at least one functional characteristic of the operational memory. A control circuit coupled to the monitor circuit is operative to generate a control signal which varies as a function of the measured characteristic of the operational memory. The memory circuit further includes a programmable voltage source coupled to the operational memory which is operative to generate at least a voltage and/or a current supplied to at least a portion of the operational memory which varies as a function of the control signal.

Abstract: In one embodiment, an improvement is described for synchronization between devices in, e.g., a wireless network, wherein at least one device includes both a slow clock and a fast clock for different modes of operation. The fast clock for an active mode of operation is calibrated after a sleep mode of operation during which the slow clock is employed for device timing. Calibration employs a filter-based technique. Counts for the slow clock and for the fast clock are measured over a first interval, and the number of slow-clock counts is measured over a second interval. An estimate for the number of fast counts over the second interval is generated, filtered to reduce noise and error effects, and then employed to update the fast clock in the active mode of operation.

Abstract: A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a single first in first out (FIFO) buffer in each serial channel is described. The RapidIO® data channel, for example, operates using a clock recovered from the data stream. The RapidIO® data stream has embedded special characters, where a select sequence of embedded characters is a clock compensation pattern. A look ahead circuit is used to detect the clock compensation pattern early and generate a clock compensation indicator signal. The FIFO writes data and the associated clock compensation indicator signal in a clock compensation indicator bit in synchronism with the recovered clock. A read circuit using a second clock of a different frequency than the first clock reads data and clock compensation bits from the FIFO and generates an almost empty signal when appropriate. A multiplexer is used at the FIFO output to pad data to the system interface.

Abstract: Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.

Abstract: Embodiments of the invention include a laser structure having a delta doped active region for improved carrier confinement. The laser structure includes an n-type cladding layer, an n-type waveguide layer formed adjacent the n-type cladding layer, an active region formed adjacent the n-type waveguide layer, a p-type waveguide layer formed adjacent the active region, and a p-type cladding layer formed adjacent the p-type waveguide layer. The laser structure is configured so that a p-type dopant concentration increases across the active region from the n-type side of the active region to the p-type side of the active region and/or an n-type dopant concentration decreases across the active region from the n-type side of the active region to the p-type side of the active region. The delta doped active region provides improved carrier confinement, while eliminating the need for blocking layers, thereby reducing stress on the active region caused thereby.

Abstract: A medium-reservation mechanism improves transmission efficiency in a multiple-channel network that includes stations with limited-selectivity receivers. The mechanism employs a medium-request signal that conveys channel information. In this network, stations check the channel information in the medium-request signal to decide whether or not to comply with the medium-request signal. If the channel information identifies the channel that is close to the channel that the station is presently operating on, the station then complies with the medium-request signal. If the channel information identifies a channel other than the channel that the station is presently operating on, the station ignores the medium-request signal.

Abstract: In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between the VNUs and CNUs using a number r of combinations of permutators, wherein each permutator combination includes (i) a cyclic shifter and (ii) a fixed, non-cyclic permutator. The cyclic shifters are capable of supporting a number p of different cyclic LDPC sub-matrices; however, when combined with different fixed permutators, the permutator combinations are capable of supporting up to r×p different LDPC sub-matrices. In other embodiments, the LDPC decoder may have fewer than r fixed permutators such that the LDPC decoder is capable of supporting between p and r×p different LDPC sub-matrices.

Abstract: In a preferred embodiment, the invention is a mobile communication device having a digital signal processor (DSP), a speaker output node, a local audio source, and an analog front-end (AFE), wherein: (1) the DSP receives a first audio signal corresponding to sound captured by a microphone near a user of the device, (2) if the device is operating in a call mode, the DSP derives a background noise signal from the first audio signal, for subtraction from the first audio signal before transmission to the AFE, and (3) if the device is operating in a non-call mode, then the DSP (i) generates a speaker output signal which substantially corresponds to the first audio signal subtracted from a local audio signal provided by the local audio source and (ii) provides the speaker output signal to a speaker via the speaker output node.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for LDPC decoding and/or error correcting. For example, various embodiments of the present invention provide LDPC decoder circuits that include a soft-input memory, a memory unit, and an arithmetic unit. The arithmetic unit includes a hardware circuit that is selectably operable to perform a row update and a column update. In such cases, a substantial portion of the circuitry of the hardware circuit used to perform the row update is re-used to perform the column update.

Abstract: A decoder (115) generates a multi channel audio signal, such as a surround sound signal, from a received first signal. The multi-channel signal comprises a second set of audio channels and the first signal comprises a first set of audio channels. The decoder (115) comprises a receiver (401) which receives the first signal. The receiver (401) is coupled to an estimate processor (405) which generates estimated parametric data for the second set of audio channels in response to characteristics of the first set of audio channels. The estimated parametric data relates characteristics of the second set of audio channels to characteristics of the first set of audio channels. The decoder (115) furthermore comprises a spatial audio decoder (403) which decodes the first signal in response to the estimated parametric data to generate the multi-channel signal comprising the second set of channels. The invention allows use of spatial audio decoding with signals that are not encoded by a spatial audio encoder.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived from a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.

Abstract: Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.

Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

Abstract: A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform at least a partial word write operation and a read operation, with the partial word write operation comprising a read phase and a write phase. The write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation by, for example, time multiplexing bitlines of the memory array within the clock cycle between the write phase of the partial word write operation and the read operation. Thus, the partial word write operation appears to a higher-level system incorporating or otherwise utilizing the memory device as if that operation requires only a single clock cycle of the memory device.

Abstract: A wireless receiver detects signals received at two or more antennas, with each antenna coupled to an input receive chain. A switch is employed to couple selected input receive chains to one or more corresponding output receive chains during listening, coarse-detection, and fine-adjustment modes. At least one channel selection filter (CSF) is employed in each output receive chain, and the receiver employs sub-ranging. During idle mode, one antenna's input receive chain is connected to two or more CSFs to detect the packet. When the packet is detected, during a coarse-adjustment mode, the CSFs are reconfigured to couple each antenna's input receive chain to a corresponding output receive chain using low-gain signals. During fine-adjustment mode, the various gains are adjusted to be either high- or low-gain to maintain signals within the dynamic range of the corresponding CSFs.