Abstract: A tracking/locating/paging system utilizes a “pre-established” local area network to determine essentially real-time information regarding one or more client devices within a closed communication environment (“pre-established” also considered as including an ad hoc network connection of devices deployed to serve a common interest). Particularly suited for arrangements such as an amusement park, college campus, shopping mall, etc., the service of the present invention utilizes conventional client devices and includes the ability to transmit an identification signal unique to each device. Various network access points distributed through the closed environment receive these unique identification signals and can therefore pinpoint the location of various client devices in real time. Accordingly, a paging function may be added to further enhance the communication aspects of the tracking and locating features of the present invention.

Abstract: In one embodiment, a method for correlating log entries in a log file to the line numbers of formatted-string output functions in source code, where the formatted-string output functions contain instructions to generate the log entries in the log file. The method includes locating the formatted-string output functions in the source code, where each formatted-string output function contains a format string. Each format string is processed to generate a corresponding regular expression to match log entries outputted by the corresponding formatted-string output function. Each regular expression is associated with the line number of the corresponding formatted-string output function. The resultant list of regular expressions and corresponding line numbers is processed with the log file, where log entries in the log file are modified to indicate the line numbers associated with matching regular expressions.

Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.

Abstract: Various embodiments of the present invention provide systems and methods for synchronizing data processing. As one example, a method for synchronizing data processing is disclosed that includes receiving a data input, and sampling the data input at a sample period to generate a sample set. A first pattern is received and a first periodic boundary associated with the first pattern is identified. In one particular case, the first pattern is a preamble pattern included as sector data on a storage medium, and the first periodic boundary is a 4T boundary. Further, a second pattern is detected in the sample that is used to establish a second periodic boundary. In one particular case, the second pattern is a SAM pattern included as sector data on a storage medium, and the second periodic boundary is a 1T boundary. Based at least in part on the first periodic boundary and the second periodic boundary, a time to transmit or assert a data-found signal is determined.

Abstract: A traffic generator generates a plurality of traffic flows, with each of the traffic flows being associatable with one or more of a plurality of output interfaces of the traffic generator. In an illustrative embodiment, each of the output interfaces may have any desired combination of the traffic flows associated therewith. The traffic flows may be generated based on user selection of at least one of a protocol encapsulation, a packet size distribution model, a packet arrival time distribution model, a traffic model, and a packet payload description. Information characterizing one or more of the traffic flows may be stored as a traffic file in a memory associated with the traffic generator.

Abstract: In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter.

Abstract: A processor circuit having reduced power consumption includes an analog front end operative to receive an analog signal supplied to the processor circuit and to generate a digital signal indicative of the analog signal. The processor further includes a digital back end operative to generate a digital output signal as a function of the digital signal generated by the analog front end. A buffer is coupled between the analog front end and the digital back end. In a first mode of operation, the digital back end operates at a substantially same data rate as the analog front end and the buffer is bypassed. In a second mode of operation, the digital back end operates at a higher data rate than the analog front end and the buffer is used to store outputs of the analog front end.

Abstract: Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L? symbols, where L? is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.

Abstract: Various systems and methods for power management are disclosed herein. For example, a synchronous semiconductor circuit is disclosed that includes two or more clock sources and a power management controller. The power management controller is operable to apply power to one of the clock sources and to select another of the clock sources for synchronization of the circuit. Then, upon stabilization of the first clock source, it is selected by the power management controller to synchronize the circuit.

Abstract: In serial communications, jitter is an unwanted variation of one or more signal characteristics. Two-dimensional modulation circuits and methods incorporate an amplitude pre-emphasis scheme as well as a transmit duty cycle pre-distortion (pre-DCD) technique to reduce jitter. The pre-DCD technique directly addresses transition edges of the data signal and is combined with amplitude pre-emphasis to improved data transmission.

Abstract: Various embodiments of the present invention provide systems and methods for sector address mark detection. As an example, data detection systems are disclosed that include a sector address mark detection circuit and a sector address mark quality detection circuit. The sector address mark detection circuit receives a data stream and identifies a sector address mark in the data stream. The sector address mark quality detection circuit receives a first sample and a second sample from the data stream corresponding to the sector address mark, and determines a quality of the sector address mark based at least in part on the first sample and the second sample. In various cases, one or more of the samples of the sector address mark up to all of the samples of the sector address mark may be used.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.

Abstract: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.

Abstract: A portable electronic device is operative to facilitate power sharing with at least a second electronic device coupled thereto. The portable electronic device includes a battery power source, a first port adapted for connection to a first network connection and a second port adapted for connection to a second network connection. An input stage in the portable electronic device is connected to the first port. The input stage is operative to supply power received from the first network connection through the first port to the battery power source for recharging the battery power source. The portable electronic device further includes an output stage connected to the second port. The output stage is operative to supply power from the battery power source to the second network connection through the second port.

Abstract: A lead-free solder joint is formed between a tin-silver-copper solder alloy (SAC), SACX, or other commonly used Pb-free solder alloys, and a metallization layer of a substrate. Interaction of the SAC with the metallization layer forms an intermetallic compound (IMC) that binds the solder mass to the metallization layer. The IMC region is substantially free of any phosphorous-containing layers or regions.

Abstract: In one embodiment, C input audio channels are encoded to generate E transmitted audio channel(s), where one or more cue codes are generated for two or more of the C input channels, and the C input channels are downmixed to generate the E transmitted channel(s), where C>E?1. One or more of the C input channels and the E transmitted channel(s) are analyzed to generate a flag indicating whether or not a decoder of the E transmitted channel(s) should perform envelope shaping during decoding of the E transmitted channel(s). In one implementation, envelope shaping adjusts a temporal envelope of a decoded channel generated by the decoder to substantially match a temporal envelope of a corresponding transmitted channel.

Abstract: A survivor path memory is provided for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state. The input processor generates a control signal that exchanges one or more pointers based on a trellis structure, wherein each of the pointers points to one of the flip flops.

Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the EA rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.

Abstract: A representative digital circuit of the invention has an on-chip, non-volatile memory, to which chip-specific speed-binning data that characterize performance of the digital circuit are written during production testing. During normal operation, the power controller that controls power-supply signals applied to the digital circuit reads the speed-binning data from the on-chip memory for use as input parameters for dynamic supply-voltage scaling, dynamic clock scaling, and/or adaptive power control that optimize (e.g., minimize) power consumption in the digital circuit. Advantageously over the prior art, the accuracy and efficiency of dynamic and/or adaptive power control arc improved because the chip-specific speed-binning data enable the power controller to better customize the power-management algorithm for the given digital circuit.

Abstract: Various systems and methods for reducing cross coupling in proximate signals are disclosed. As one example, a system for reducing cross-coupling in adjacent signals that includes an active slew rate limiter circuit is disclosed. The active slew rate limiter circuit is operable to receive an input signal, and to provide an output signal based on the input signal with a controlled slew rate. In some cases, such systems may be included within a storage device that includes a read head. In such cases, the systems may operate to assure a substantially constant power dissipation within the read head.