Abstract: The present invention enhances the dynamic frequency selection 9DFS) algorithms used in Wireless LANs by adding a channel swapping mechanism. The aim of the traditional DFS algorithm is to dynamically select channels in a wireless LAN in such a way that the best performance is achieved. However, not always the optimal channel selection is achieved. This invention describes an addition to the DFS algorithm in such a way that two APs can decide to swap channels instead of one AP switching to another channel. To avoid the problem of sub-optimal channel selection, a requesting AP sends Swap Requests to other APs in order to sense the willingness of other APs to swap channels with the requesting AP.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a method for data regeneration is disclosed that includes receiving a data input derived from a medium, determining a media defect corresponding to the data input, and determining an attenuation factor associated with the defective medium. Based at least in part on the determination that the medium is defective, amplifying the data input by a derivative of the attenuation factor to regenerate the data.

Abstract: In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal.

Abstract: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.

Abstract: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors.

Abstract: An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.

Abstract: In one embodiment, a virtual gateway mediates between a dual-mode subscriber device and an IP-based PBX. In particular, the virtual gateway includes a WLAN interface for communicating with the dual-mode subscriber device and a network interface (wired or wireless) for communicating with the IP-based PBX over the Internet. As such, the virtual gateway may relay voice and call control instructions between the dual-mode subscriber device and the IP-based PBX, and may provide the same call control functions to the dual-mode subscriber device provided by the call control processor in existing dual-mode phones. The embodiment further provides a dual-mode subscriber device suitable for operation with the virtual gateway. Because the dual-mode subscriber device does not require a call control processor, the battery life and cost of the device are significantly improved.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: In accordance with exemplary embodiments, a multi-level flash memory employs error correction of systematic errors when reading multi-level flash memory. Error correction includes i) detection of each systematic error, ii) feedback of the systematic error to circuitry within the memory, and iii) subsequent adjustment within that circuitry to cause a correction of systematic error in the output signal of the multi-level flash memory.

Abstract: In one embodiment, the present invention generates a single rotation angle that may be used to maximize diversity of a quasi-orthogonal space-time block code that encodes groups of four data symbols. Two rotation angles corresponding the first two data symbols in a group are set to zero, and two rotation angles corresponding to the second two data symbols in a group are set to a single initial value. A codeword distance matrix is determined for each possible combination of codewords and erroneously decoded codewords that may be generated using the initial rotation angle, and the minimum of the determinants of these matrices is selected. This process is repeated to generate a plurality of minimum determinants, and, for each iteration, a different single rotation angle corresponding to the second two data symbols is used. Then, a single rotation angle is selected that corresponds to the maximum of the minimum determinants.

Abstract: Methods and apparatus are provided for storing survivor paths in a Viterbi detector. The invention maintains at least one register and at least one pointer for each state. Each register stores a bit sequence associated with a Viterbi state and each pointer points to one of the registers. One or more predefined rules based on a trellis structure are employed to exchange one or more of the pointers. A survivor path memory is also disclosed for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state.

Abstract: Proximity regulation systems for use with a portable cell phone and portable cell phones are disclosed. In one embodiment, a portable cell phone includes a proximity regulation system having a location sensing subsystem configured to determine a location of a portable cell phone proximate a user by determining a mode of operation of the portable cell phone. A power governing subsystem is coupled to the location sensing subsystem and configured to determine a proximity transmit power level of the portable cell phone based on the location.

Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Abstract: Various embodiments of the present invention provide circuits and methods for improved FET matching. As one example, such methods may include providing two or more transistors. Each of the transistors includes a channel that varies in cross-sectional width from the source to the drain, and the transistors are matched one to another.

Abstract: A system or method for communicating data over a voice channel between a transmitter and a receiver. In one embodiment, the system includes: (1) a silence detector, coupled to the transmitter, that identifies a pause in voice traffic that is to be transmitted over the voice channel and generates an interjection signal during the pause and (2) a data injector, coupled to the silence detector, that receives the interjection signal and responds by causing the transmitter to transmit data to the receiver over the voice channel.

Abstract: A method of using an intercom on a cordless telephone during an active call. The active call is put on hold while the intercom is in use. Once the call is re-activated, the intercom is shut off. This system may be designed for a cordless telephone with one handset or a plurality of handsets.

Abstract: In one embodiment, a powered device (PD) (402) has a PHY module (410) and a media access controller (419) (MAC), the PD (402) adapted to connect to power sourcing equipment (PSE) via a cable, (408) where the PD (402) is adapted to communicate with and receive power from the PSE via the cable, in accordance with the Power-over-Ethernet (PoE) standard. The PD (402) extracts (413) from the cable (408) a DC signal used to power the PD without using a transformer. Capacitors (420) located in the signal paths between the MAC (419) and the cable (408) support electrical isolation of the MAC (419).

Abstract: In a communication system comprising a link layer device connectable to one or more physical layer devices, the link layer device is configured using an efficient shared architecture for processing data associated with a plurality of links including at least one ingress link and at least one egress link. The link layer device comprises an ingress data clock processor configured to generate an ingress clock signal for processing data associated with said at least one ingress link, an egress data clock processor configured to generate an egress clock signal for processing data associated with said at least one egress link, and a control and configuration unit shared by the ingress data clock processor and the egress data clock processor. Another aspect of the invention relates to a buffer adaptive processor that in an illustrative embodiment limits clock variability in the presence of cell delay variation or cell loss.

Abstract: Methods and apparatus are provided for communicating data in a multiple antenna communication system having N transmit antennas. According to one aspect of the invention, a header format includes a legacy preamble having at least one legacy long training field and an extended portion having at least N additional long training fields on each of the N transmit antennas, wherein one or more of the at least N additional long training fields are comprised of only one Orthogonal Frequency Division Multiplexing (OFDM) symbol. The extended portion optionally comprises one or more repeated OFDM symbols for frequency offset estimation. In one implementation, the extended portion comprises a first high throughput long training field comprised of two repeated OFDM symbols and N?1 high throughput long training fields comprised of only one OFDM symbol. In another variation, the extended portion comprises N high throughput long training fields comprised of only one OFDM symbol.