Abstract: Duplex audio communications over a network use compressed audio data, with linear prediction coefficients (LPCs) and variances by which sample values differ from predictions. A adaptive echo canceller for a transceiver develops finite impulse response filter (FIR) coefficients characterizing an echo path between its local audio output and audio input. The received/decompressed audio data is applied to the FIR coefficients, and the predicted echo is subtracted from the uplink signal. Echo is detected as cross-correlation of the receive signal versus the uplink/send signal over time. In one embodiment, the cross-correlation is determined using a pre-whitened receive signal, obtained by adopting the variance values received over the network by the downlink Codec. Apart from the uplink Codec, no speech analysis filter or process is needed. The technique is apt for GSM, AMR and similar compressed audio communications.

Abstract: Methods and apparatus are provided for reduced complexity Soft-Output Viterbi detection. A Soft-Output Viterbi algorithm processes a signal by determining branch metrics using a branch metrics unit; determining survivor paths for sequence detection using a first add-compare select unit; and determining survivor paths for generating one or more bit reliability values using a second add-compare select unit, wherein the first and second add-compare select units process the branch metrics determined by the branch metrics unit. The first and second add-compare select units can optionally process branch metrics having a different number of bits.

Abstract: A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.

Abstract: The disclosure provides a wireless device for use in a wireless network, systems and methods for identifying radar signals and for giving the wireless network a radar-avoidance capability. In one embodiment, the wireless device includes: (1) a pulse analyzer configured to make a determination whether a received pulse is a radar pulse and not a wireless network pulse and (2) a pulse reporter coupled to the pulse analyzer and configured to generate, if the determination is positive, a report thereof for transmission over the wireless network to a central aggregation node thereof.

Abstract: A mobile communication device and a camera module are disclosed herein. In one embodiment, the mobile communication device includes: (1) a main body having attaching means for attaching a camera module, the attaching means comprising means for automatically moving the camera module from the retracted position to the exposed position employing electrical energy and (2) a camera module having complementary attaching means to the main body, such that the camera module is movable with respect to the main body from a retracted position to an exposed position, is wholly detachable from the mobile communication device and is rotatable in the exposed position about at least one axis of rotation.

Abstract: A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory.

Abstract: Various systems and methods for peak signal detection. As one example, a method for peak signal detection that includes receiving a signal is disclosed. The received signal includes a signal region where the signal is increasing in amplitude, another signal region where the signal is decreasing in amplitude, and a transitional signal region coupling the first two signal regions. In some cases, the transitional region is of zero duration and the signal transitions directly from the increasing region to the decreasing region. The method further include calculating a distance between the signal region of increasing amplitude and the signal region of decreasing amplitude, and determining a peak of the received signal that is one half the distance from the signal region of increasing amplitude.

Abstract: A method, arithmetic divider unit, and system are disclosed for dividing a dividend DZM . . . Z0 having a most significant bit ZM and a plurality of less significant bits ZM?1 through Z0 by a divisor RZN . . . Z0 having a most significant bit ZN and a plurality of less significant bits ZN?1 through Z0. The method, arithmetic divisor unit, and system round the divisor to the next significant bit greater than the divisor's most significant bit ZN to produce a first partial divisor RZN+1, divide the dividend DZM . . . Z0 by the first partial divisor RZN+1 to produce a first partial quotient QN, calculate one or more additional partial quotients based on one or more divisor bits selected from the plurality of divisor bits ZN?1 through Z0, and add the first partial quotient QN and one or more additional partial quotients to produce an estimated final quotient.

Abstract: In one embodiment, a low cost, simple circuit for detecting an off-hook condition of a telecommunication line comprising tip and ring signal lines is provided. The circuit comprises a voltage divider for coupling between the tip and ring lines without an intervening transistor and having a node at which is presented a scaled version of a voltage across the voltage divider. The circuit further comprises a transistor having a control terminal coupled to the node, a first current flow terminal coupled to a voltage source, and a second current flow terminal coupled to an output terminal, wherein the output terminal bears a value that is indicative of a voltage across the tip and ring lines and thus whether the telecommunication line is off-hook.

Abstract: Various embodiments of the present invention provide systems and methods for improved timing recovery. As one example, some embodiments of the present invention provide timing recovery circuits that include an error signal and a digital phase lock loop circuit. The error signal indicates a difference between the predicted sample time and an ideal sample time. The digital phase lock loop is operable to apply an adjustment value such that a subsequent sample time is moved toward the ideal sample time. Further, the digital phase lock loop circuit includes an adjustment limit circuit that is operable to limit the adjustment value.

Abstract: Described embodiments provide a method and system for signal compensation in a SERDES communication system that includes monitoring the quality of a data signal after passing through a transmission channel. The quality of the data signal is monitored with at least one of a BER calculation algorithm and a received eye quality monitoring algorithm. Variations in channel length of the transmission channel are compensated for by i) adjusting a length of transmission line delay of the data signal from the transmission channel, ii) comparing the data signal quality with a threshold for the adjusted data signal; and iii) repeating i) and ii) until the data signal quality meets the threshold.

Abstract: In an illustrative embodiment, a memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold voltage represents a first stored logic value. By determining which one of the first and the second MOSFETs has an altered threshold voltage, the stored logic value is determinable. The threshold voltage of the first MOSFET is altered by supplying current through a MOSFET gate, causing a gate heating effect that results in a threshold voltage shift.

Abstract: An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

Abstract: The invention, in one aspect, provides a semiconductor device that includes a collector for a bipolar transistor located within a semiconductor substrate and a buried contact, at least a portion of which is located in the collector to a depth sufficient that adequately contacts the collector.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for out of band detection. As one example, an out of band detection circuit is disclosed that includes an input signal, a clock generation circuit, and a sampling circuit. The clock generation circuit receives the input signal and derives therefrom a sampling clock, and the sampling circuit is operable to sample the input signal at a time indicated by the sampling clock.

Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Abstract: In described embodiments, an adaptive equalizer employed by a receiver in a communication channel, such as Fibre Channel, employs pattern recognition. When a repeating pattern, such as an IDLE or ARBFF pattern, is employed by a standard to, for example, maintain a communication link, an equalizer of the receiver might adaptively set its equalizer parameters based on characteristics of the signal energy of the repeating pattern rather than adaptively set its equalizer parameters based on characteristics of the signal energy of generally random user data carried on the link. Pattern recognition by the receiver allows for maintaining adaptive equalizer parameters at settings preferred for data detection of the typical random data, improving data detection performance of the receiver when the channel transitions from a preset or synchronization repeating pattern to a user random data pattern.

Abstract: A conventional serial communications protocol that is limited to supporting only host-to-slave communications, such as SATA or SAS, is extended to support peer-to-peer communications, e.g., by adding a memory-map layer into the conventional protocol stack between the link layer and the protocol layer. The addition of the memory-map layer enables two (or more) non-host devices (i.e., peer devices) to communicate with one another without using a host computer and without relying on conventional protocol-bridging techniques.

Abstract: Various apparatuses and methods for offsetting the phase and/or frequency of a clock signal are disclosed herein. For example, some embodiments provide an apparatus for generating a clock signal, including a quadrature delay circuit connected to an input clock signal. The quadrature delay circuit outputs components of the input clock signal with different phase shifts. A first amplitude modulator is connected to the first output of the quadrature delay circuit, and a second amplitude modulator is connected to the second output of the quadrature delay circuit. A summer combines the output of the first and second amplitude modulators.

Abstract: In described embodiments, an adaptive equalizer employed by a receiver in a communication channel, such as Fiber Channel, employs pattern recognition. When a repeating pattern, such as an IDLE or ARBFF pattern, is employed by a standard to, for example, maintain a communication link, an equalizer of the receiver might adaptively set its equalizer parameters based on characteristics of the signal energy of the repeating pattern rather than adaptively set its equalizer parameters based on characteristics of the signal energy of generally random user data carried on the link. Pattern recognition by the receiver allows for maintaining adaptive equalizer parameters at settings preferred for data detection of the typical random data, improving data detection performance of the receiver when the channel transitions from a preset or synchronization repeating pattern to a user random data pattern.