Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.

Abstract: Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.

Abstract: A multi-stage receiver including, in one embodiment, a sequence of processing stages. At least one of the processing stages includes a first processing block, a delay block, and a second processing block. The first processing block is adapted to receive an input signal and generate from the input signal one or more processing parameters. The delay block is adapted to generate a delayed signal. The second processing block is adapted to apply the one or more processing parameters to the delayed signal to generate an output signal. The delay block compensates for one or more processing delays associated with the generation of the one or more processing parameters by the first processing block.

Abstract: Multi-dimensional finite impulse response filters ale disclosed in hybrid and transpose forms. Multi-dimensional signals can be expressed in a vector (ox matrix) form to allow multi-dimensional signals to be processed collectively. Known hybrid and transpose FIR filters are extended to the multi-dimensional case to allow multi-dimensional signals to be processed with reduced redundancies. The input signals are vectors with multidimensional components. The disclosed FIR filters include multipliers that perform matrix multiplications with multiple coefficients, and adders for performing vector additions with multiple inputs and outputs. The z-transforms are provided for the disclosed hybrid and transpose multi-dimensional FIR filters.

Abstract: Methods and apparatus are provided for digital linearization of an analog phase interpolator. Up to 2N desired phase values are mapped to a corresponding M bit value, where M is greater than N. A corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2N desired phase values. A linearized phase interpolator is also provided that accounts for process, voltage, temperature or aging (PVTA) variations.

Abstract: In one embodiment, a low cost, simple circuit for detecting an off-hook condition of a telecommunication line comprising tip and ring signal lines is provided. The circuit comprises a voltage divider for coupling between the tip and ring lines without an intervening transistor and having a node at which is presented a scaled version of a voltage across the voltage divider. The circuit further comprises a transistor having a control terminal coupled to the node, a first current flow terminal coupled to a voltage source, and a second current flow terminal coupled to an output terminal, wherein the output terminal bears a value that is indicative of a voltage across the tip and ring lines and thus whether the telecommunication line is off-hook.

Abstract: A network or other type of processor operates to switch packets from an incoming cell stream to an outgoing cell stream. Each received and transmitted cell in a cell stream includes portions of packets, or complete packets or both. Packets are reassembled from incoming cells, and outgoing cells may be created from portions of packets, complete packets or both. The packets in the outgoing cells may be from incoming packets, switched reassembled packets or both. Each incoming and outgoing cell is associated with one virtual channel, and each virtual channel for an outgoing cell may be different from the virtual channel corresponding to the incoming cell or cells from which a packet was reassembled. Switched packets also may have their conversation identifications changed. Partial packets or partial cells that are awaiting completion are retained such that switching capabilities associated with the virtual channel and channel identification modifications may be used.

Abstract: A packet processing system comprises first processing circuitry for performing a first function, and first memory circuitry coupled to the first processing circuitry for storing received packets, wherein at least a portion of the packets stored by the first memory circuitry are usable by the first processing circuitry in accordance with the first function. The packet processing system further comprises at least second processing circuitry for performing a second function, and at least second memory circuitry coupled to the second processing circuitry for storing at least a portion of the same packets stored in the first memory circuitry, wherein at least a portion of the packets stored in the second memory circuitry are usable by the second processing circuitry in accordance with the second function. In an illustrative embodiment, the first processing circuitry and the second processing circuitry operate in a packet switching device such as a router.

Abstract: An electronic device, comprising a semiconductor substrate having a first metal pad formed thereover, a device package substrate having a second metal pad formed thereover, and, a doped solder bump. The doped solder bump is located between and in contact with said first and second metal pads. The doped solder bump consisting of Sn, one or both of Ag and Cu, and a fourth row transition metal dopant in a concentration range from 0.35 wt. % to 2 wt. %.

Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.

Abstract: An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

Abstract: A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The decoder buffer level limits are specified in terms of a maximum number of encoded frames (or duration). The transmitter can predict the number of encoded frames, Fpred, in the decoder buffer and transmit the value, Fpred, to the receiver with the audio data. If the transmitter determines that the decoder buffer level is becoming too high, the frames being generated by the encoder are too small and additional bits are allocated to each frame for each of the N programs. Likewise, if the transmitter determines that the decoder buffer level is becoming too low, the frames being generated by the encoder are too big and fewer bits are allocated to each frame for each of the N programs. The transmitted predicted buffer level, Fpred, can also be employed to (i) determine when the decoder should commence decoding frames; and (ii) synchronize the transmitter and the receiver.

Abstract: Techniques are provided for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. A reduced state sequence estimation (RSSE) decoder is provided for a multidimensional code. A multidimensional code symbol comprises a number of symbol components of lower dimensionality. The RSSE decodes comprises at least one branch metric unit that calculates branch metrics for a received signal based on intersymbol interference and intrasymbol interference estimates, the at least one branch metric unit compensating for intrasymbol interference caused by symbol components within a current multidimensional code symbol; and a decision feedback unit that processes survivor symbols to calculate the intersymbol interference estimates for different code states of the multidimensional code and channels used to transmit the multidimensional code.

Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ?? rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.

Abstract: A video delivery system and service for use with a video presentation and methods of delivering and receiving a video representation. In one embodiment, a method of receiving a video representation includes receiving a request to program a video viewing device to record a video presentation employing a selected content. The method also includes remotely programming the video viewing device employing the selected content to provide the video representation.

Abstract: Various embodiments of the present invention provide systems, methods and media formats for efficiently determining a position error of a head in relation to a storage medium. In one case, a system is disclosed that includes a storage medium with a series of data. The series of data includes a first defined marker and a second defined marker located a distance from the first defined marker, and position location data. The systems further include a first detector circuit that is operable to detect the first defined marker and to establish a location of the first defined marker, and a second detector circuit that is operable to detect the second defined marker and to establish a location of the second defined marker. The systems further include an error calculation circuit and an interpolation circuit. The error calculation circuit is operable to calculate an interpolation offset based at least in part on the location of the first defined marker and the location of the second defined marker.

Abstract: Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoder is provided for encoding message symbols, m0 through mN-1, to generate a codeword that includes the message symbols, m0 through mN-1, and one or more check symbols. The error correction encoder comprises a linear feedback shift register having one or more flip-flops to generate the check symbols after shifting the message symbols, m0 through mN-1, through the linear feedback shift register. An error correction decoder is also provided for decoding a codeword that includes message symbols, m0 through mN-1, and one or more check symbols. The error correction decoder comprises a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting the message symbols, m0 through mN-1, and the one or more check symbols through the linear feedback shift register.

Abstract: In a system including a processor and memory coupled to the processor, a method of device failure analysis includes the steps of: upon each error detected within a test series performed on a device, the processor storing within a table in the memory an address at which the error occurred in the device and storing a bit position of each failed bit corresponding to that address; for each unique address at which at least one error occurred, determining how many different bit positions corresponding to the address failed during the test series; and based on results of the test series, determining whether the device failed the test series.

Abstract: Techniques are disclosed for automatic generation of a location-indicative instruction displayable to one or more users in a communication system which includes a wireless network comprising a plurality of user devices adapted for communication with at least one access point device. A test of a communication link between at least one of the user devices and the access point device is initiated. Based at least in part on a result of the test, an instruction displayable to a user associated with a given one of the user devices is generated, the instruction being indicative of a location at which the given user device is expected to obtain a particular level of data throughput performance.

Abstract: In accordance with the principles of the present invention utilizing the BLUETOOTH specification Cordless Telephony profile, incoming calls to a cell phone including a Gateway role can be routed to another piconet device (e.g., another cell phone including a Terminal role. Two cell phones with BLUETOOTH capability each include the Cordless Telephony Profile. The cell phone receiving the call acts as a PSTN cordless telephone Gateway cell phone via the cellular network, while the other cell phone acts as a cordless telephone Terminal cell phone. The cordless telephone Terminal cell phone then acts as an extension to the Gateway cell phone allowing both calls to the Gateway cell phone to be answered at the Terminal cell phone, and even allowing calls by the Gateway cell phone to be originated by the Terminal cell phone.