Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Abstract: A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The transmitter predicts the number of encoded frames, Fpred, in the buffer having a limited level and transmits the value, Fpred, to the receiver with the frame. If the transmitter determines that the decoder buffer level is high, the frames being generated by the encoder are small and additional bits are allocated to each frame for each of the N programs. Likewise, if the transmitter determines that the decoder buffer level is becoming low, the frames being generated by the encoder are big and fewer bits are allocated to each frame for each of the N programs. The transmitted predicted buffer level, Fpred, can also be employed to (i) determine when the decoder should commence decoding frames; and (ii) synchronize the transmitter and the receiver clock using feedback depending on the compared level of the decoder to the actual level to Fpred.

Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Abstract: Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Abstract: An integrated circuit device for use in a line card of a network node of a digital networking system is provided. The integrated circuit device is capable of intercepting one or more control messages from at least one CPE device. The one or more control messages correspond to at least an operational status of at least one TE device associated with the at least one CPE device. The integrated circuit device is also capable of transmitting one or more rate control messages to a network processor of the network node to adapt bandwidth utilization and provide adapted data traffic flow to at least one CPE device in relation to the operational status of the at least one TE device.

Abstract: Methods and apparatus are provided for counter-based digital frequency lock detection. A counter-based digital frequency lock detector in accordance with the present invention comprises a reference counter clocked by a reference clock and a target counter clocked by a target clock. The target counter is n bits and n is less than a number of bits of the reference counter. A frequency offset violation of the target clock is detected by comparing a value of the target counter to an n bit counter.

Abstract: Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft output channel detector is provided that operates at a rate of 1/N and detects N bits per 1/N-rate clock cycle. The channel detector comprises a plurality, D, of MAP detectors operating in parallel, wherein each of the MAP detectors generates N/D log-likelihood ratio values per 1/N-rate clock cycle and wherein at least one of the plurality of MAP detectors constrains each of the bits. The log-likelihood ratio values can be merged to form an output sequence. A single MAP detector is also provided that comprises a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ different trellis structures.

Abstract: An audio device includes a Bluetooth receiver, a Bluetooth transmitter, a speaker and a housing. The Bluetooth receiver is capable of wirelessly receiving signals in at least two audio channels. The Bluetooth transmitter is capable of wirelessly retransmitting at least a first one of the two audio channels. The speaker plays the second one of the two audio channels. The housing contains the Bluetooth receiver, the Bluetooth transmitter, and the ear phone. The housing is shaped to fit in or on an ear of a user.

Abstract: A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.

Abstract: A processor configured to operate with multiple operation codes for each of a plurality of instructions comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is configured to decode a first operation code to produce a given one of the instructions and to decode a second operation code different than the first operation code to also produce the given instruction. Thus, the same instruction is produced for execution by the processing circuitry regardless of whether the first operation code or the second operation code is decoded. The assignment of multiple operation codes to a given instruction may occur in conjunction with the design of the processor, and dynamic selection of a particular one of those operation codes may be performed in conjunction with assembly of code for execution by the processor.

Abstract: Methods and apparatus are provided for per-antenna training in a multiple antenna communication system having a plurality of transmit antenna branches. A long training sequence is transmitted on each of the transmit antenna branches such that only one of the transmit antenna branches is active at a given time. The active transmit antenna branch is configured in a transmit mode during the given time and one or more of the inactive transmit antenna branches are configured in a receive mode during the given time. The transmit and receive modes are configured, for example, by applying a control signal to one or more switches.

Abstract: Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame marker and a predefined binary value in an output of the logic function.

Abstract: A laser assembly comprises a substrate, one or more standoffs and a semiconductor laser. The substrate has a first doped region and a second doped region. The second doped region is proximate to an upper surface of the substrate and forms a pn junction with the first doped region. The semiconductor laser is operative to emit light from an upper surface and a lower surface. Moreover, the semiconductor laser is attached to the upper surface of the substrate with the one or more standoffs such that the light emitted from the lower surface of the semiconductor laser impinges on the second doped region.

Abstract: A multicast group list (i.e., destination node address list) for a network device is circularly linked such that the list can be entered at any point and traversed back to the entry point. The list traversal is then terminated as the entire list has been processed. The data packet received at the network device for transmission to the multicast group can indicate the entry point, although there are other techniques for determining the entry point. The destination node address for the entry point is skipped, that is the multicast data packet is not transmitted to the entry point destination address.

Abstract: A method of using an intercom on a cordless telephone during an active call. The active call is put on hold while the intercom is in use. Once the call is re-activated, the intercom is shut off. This system may be designed for a cordless telephone with one handset or a plurality of handsets.

Abstract: A delay circuit having reduced duty cycle distortion is provided. The delay circuit includes a plurality of delay elements connected together in a series configuration. Each of the delay elements has a prescribed delay associated therewith. The delay circuit further includes a controller connected to respective outputs of the delay elements. The controller is configured such that signal paths between the respective outputs of the delay elements and an output of the controller have delays that are substantially the same relative to one another. Each of the signal paths has a tri-statable switching element associated therewith.

Abstract: In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level of at least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter.

Abstract: An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology.

Abstract: The invention relates to a detection method using a receiver of a digital communication system for the detection of a symbol from a received signal, which signal is transmitted by a transmitter of the digital communication system, wherein the symbol is a selected symbol out of a predetermined set of symbols and wherein each symbol of the predetermined set comprises a sequence of chips wherein each of the chips is PSK-modulated according to a selected modulation code.