Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.

Abstract: In one embodiment, a method for processing a series of MAC-hs protocol data units (PDUs) in an HSDPA-compatible (high-speed downlink packet access) receiver in a 3G wireless communication network, the method including: (a) receiving a MAC-hs PDU having: (i) a queue identification (QID), (ii) a transmission sequence number (TSN), and (iii) one or more MAC-d PDUs, (b) then disassembling the MAC-hs PDU (c) then distributing the one or more MAC-d PDU to a reordering queue indicated by the QID, and (d) then performing reordering processing for the corresponding reordering queue based on the TSN. Steps (a) and (b) are performed in a physical layer of the receiver. Steps (c) and (d) are performed in a data-link layer of the receiver.

Abstract: A method and device for providing a communication session with a plurality of users. In one embodiment, the method includes: (1) transmitting an initiation message from the first terminal to the second terminal, the initiation message including a first address assigned to the first terminal, (2) dividing a display of the first terminal to simultaneously display text to be transmitted from the first terminal and text received from the second terminal, the dividing based on if there is text to be transmitted by the first terminal, (3) receiving the initiation message at the second terminal, (4) transmitting a first reply to the initiation message from the second terminal to the first terminal and (5) receiving the first reply at the first terminal.

Abstract: A cache memory architecture, a method of operating a cache memory and a memory controller. In one embodiment, the cache memory architecture includes: (1) a segment memory configured to contain at least one most significant bit (MSB) of a main memory address, the at least one MSB being common to addresses in a particular main memory logical segment that includes the main memory address, (2) a tag memory configured to contain tags that include other bits of the main memory address and (3) combinatorial logic associated with the segment memory and the tag memory and configured to indicate a cache hit only when both the at least one most significant bit and the other bits match a requested main memory address.

Abstract: An electronic device includes a metallic conducting lead having a surface. A pre-solder coating over the surface consists essentially of tin and one or more dopants selected from Al or a rare earth element.

Abstract: In one embodiment, a receiver comprises an automatic gain controller (AGC), an equalizer, a controller, and a register interface. The AGC makes gain adjustments to compensate for changes in the average amplitude of a received signal. The equalizer has a coefficient updater that calculates coefficients and a finite impulse response (FIR) filter that applies the coefficients to the received signal to generate an equalized signal. During gain adjustments by the AGC, the register interface provides a weight freeze signal to the coefficient updater, which subsequently freezes the updating of the coefficients for a freeze duration period. Then, register interface provides a scaling factor, generated by the controller based on the size of the gain adjustment, to the coefficient updater. At the end of the freeze period, coefficient updater applies the scaling factor to the coefficients and unfreezes the coefficient updating.

Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

Abstract: A wireless telecommunication device conducts base station pages at large intervals, such as 30 seconds, rather than the more conventional 0.5 to 4 seconds. The network processes calls placed to that telecommunication device in accordance with an SMS (Short Messaging Service) type protocol rather than a conventional voice call protocol. Particularly, the network sends an SMS to the telephone indicating that a third party is calling (hereinafter termed a “pre-call SMS”). The pre-call SMS indicates the telephone number of the third party. The user of the telephone may call the third party back. In accordance with this protocol, the need to page at very short intervals so as to permit a telephone call to be established in “real-time” is eliminated. Therefore, the paging interval can be increased substantially, thereby substantially prolonging battery charge lifetime of the telephone.

Abstract: Methods and apparatus are provided for direct synthesis of RF signals using a delta-sigma modulator. An RF signal is synthesized from an input signal by quantizing the input signal using a quantizer, such as a one bit quantizer; determining a quantization error associated with the quantizer; generating an error prediction value using an error predictive filter, wherein the error predictive filter comprises one or more filter zeroes on a unit circle for one or more desired frequencies of f1, f2, . . . fn and one or more filter poles having a magnitude inside the unit circle and a frequency substantially equal to the one or more desired frequencies of f1, f2, . . . fn; and subtracting the error prediction value from the input signal. The filter poles have a magnitude that reduces a boost provided out-of-band.

Abstract: A method of isolating piezoelectric thin film acoustic resonator devices to prevent laterally propagating waves generated by the device from leaving the device and/or interfering with adjacent devices or systems. Specifically, this isolation technique involves the manipulation or isolation of the piezoelectric material layer between the acoustic resonator devices, in an effort to limit the amount of acoustic energy which propagates in a lateral direction away from the device. In one aspect, at least a portion of the piezoelectric material not involved in signal transmission by transduction between RF and acoustic energy is removed from the device. In another aspect, the growth a piezoelectric material is limited to certain regions during fabrication of the device. In a further aspect, the crystal orientation of the piezoelectric material is disrupted or altered during device fabrication so as to form regions having excellent piezoelectric properties and regions exhibiting poor piezoelectric characteristics.

Abstract: A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols and subtracts the intersymbol interference from the received signal. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol.

Abstract: Described embodiments include a level shifter that provides a voltage level shift to applied signals, the amount of voltage shift being accurately controlled and independent of PVT. The level shifter has first transistor configured as a voltage follower with the gate coupled to an input terminal of the shifter and the source coupled to a node, a diode-connected transistor coupled between the node and an output terminal of the circuit, a first controlled current source coupled to the node, and a second controlled current source coupled to the output terminal. A controller receives a bandgap-stabilized voltage, squares the stabilized voltage to produce a control signal that controls the first and second controlled current sources. The voltage shift is proportional to a digitally-controlled scale factor (K) times the stabilized voltage. The ratio of the current from the first current source to the second current source is (K+1)/K.

Abstract: Methods and apparatus are provided for communicating data in a multiple antenna communication system having N transmit antennas. According to one aspect of the invention, a header format includes a legacy preamble having at least one legacy long training field and an extended portion having at least N additional long training fields on each of the N transmit antennas. The N additional long training fields may be tone interleaved across the N transmit antennas and are used for MIMO channel estimation. The extended portion may include a short training field for power estimation. The short training field may be tone interleaved across the N transmit antennas and have an extended duration to support beam steering.

Abstract: A method for controlling a transmission rate of at least one transceiver, the transceiver including a transmitter and a receiver, includes: determining a signal quality characteristic corresponding to a signal received at the receiver by measuring a difference between one or more reference constellation points and one or more received constellation points, and modifying a transmission rate of the transmitter over a wireless communication channel as a function of the signal quality characteristic.

Abstract: Described embodiments provide rate setting for nodes of a scheduling hierarchy of a network processor. The scheduling hierarchy is a tree structure having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A traffic manager queues received tasks in a queue of the scheduling hierarchy associated with a data flow of the task. The queue has a parent scheduler at each level of the hierarchy up to the root scheduler. A scheduler selects a child node for transmission based on a number of arbitration credits in an arbitration credit bucket of each child. An arbitration credit value is determined for each child by maintaining a time stamp value corresponding to a time value of a previous selection of the child node and determining an elapsed time value based on the time stamp value and a current time value, scaled by a scaling factor.

Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.

Abstract: An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology.

Abstract: The present invention provides method of manufacture for a printed wiring board. The printed wiring board constructed according to the teachings of the present invention includes a printed wiring board dielectric layer having conductive foils located on at least two sides thereof. The printed wiring board further includes a solid core conductive material interconnecting the conductive foils.

Abstract: In one embodiment, a signal-processing receiver has an upstream processor and a low-density parity-check (LDPC) decoder for decoding LDPC-encoded codewords. The upstream processor generates a soft-output value for each bit of the received codewords. The LDPC decoder is implemented to process the soft-output values without having to wait until all of the soft-output values are generated for the current codeword. Further, the LDPC code used to encode the codewords is arranged to support such processing. By processing the soft-output values without having to wait until all of the soft-output values are generated for the current codeword, receivers of the present invention may have a lower latency and higher throughput than prior-art receivers that wait until all of the soft-output values are generated prior to performing LDPC decoding. In another embodiment, the LDPC decoder processes the soft-output values as soon as, and in the order that, they are generated.

Abstract: A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.