Abstract: Roughly described, a packet switching fabric contains a separate queue scheduler for each combination of an input module and a fabric output port. The schedulers may also be specific to a single class of service. Each queue scheduler schedules its packets without regard to state of other input queues and without regard to packets destined for other output ports. In an aspect, the fabric manages per-flow bandwidth utilization of output port bandwidth capacity by monitoring the same and asserting backpressure toward the queue scheduler for any thread that is exceeding its bandwidth allocation. In another aspect, a switching fabric uses leaky buckets to apply backpressure in response to overutilization of downstream port capacity by particular subflows. In another aspect, a switching fabric includes a cascaded backpressure scheme.

Abstract: The invention, in one aspect, provides a method of manufacturing a semiconductor device. This method includes providing a semiconductor substrate and depositing a metal layer over the semiconductor substrate that has an overall thickness of about 1 micron or greater. The metal layer is formed by depositing a first portion of the thickness of the metal layer, which has a compressive or tensile stress associated therewith over the semiconductor substrate. A stress-compensating layer is deposited over the first portion, such that the stress-compensating layer imparts a stress to the first portion that is opposite to the compressive or tensile stress associated with the first portion. A second portion of the thickness of the metal layer is then deposited over the stress-compensating layer.

Abstract: An assembly comprises a stiffener, a circuit substrate and an IC chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers at least a portion of the first region of the stiffener, while the IC chip overlies at least a portion of each of the first and second regions of the stiffener. The assembly further comprises a signal solder bump and a thermally conductive feature. The signal solder bump contacts the IC chip and the circuit substrate. The thermally conductive feature is disposed between, and is metallurgically bonded to, the integrated circuit chip and the second region of the stiffener. The thermally conductive feature provides an efficient thermal conductivity pathway between the IC chip and the stiffener.

Abstract: An improved multi-channel receiver for satellite broadcast applications or the like. In an exemplary embodiment, a primary AGC loop controls an analog sub-receiver adapted to simultaneously receive multiple signals. Multiple digital demodulators, coupled to the sub-receiver, demodulate the multiple received signals. Multiple secondary AGC loops, one for each received signal, compensate for variations in demodulated signal strengths caused by the primary AGC loop. A feed-forward AGC compensation technique generates scalar control values for scaling the demodulated signals before the demodulated signals are processed by the secondary AGC loops. This at least partially compensates for gain variations caused by the primary AGC, reducing received signal drop-outs before the secondary AGC loops can compensate for the gain variations.

Abstract: Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.

Abstract: A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values.

Abstract: A system (10) for monitoring and controlling a fabrication process includes at least a first subsystem (12), a crystallographic analysis subsystem (14), and a second subsystem (16), wherein the first subsystem and second subsystem perform respective fabrication steps on a workpiece. The crystallographic analysis subsystem may be coupled to both the first subsystem and second subsystem. The analysis subsystem acquires crystallographic information from the workpiece after the workpiece undergoes a fabrication step by the first subsystem and then provides information, based on the crystallographic information acquired, for modifying parameters associated with the respective fabrication steps. The system may also include neural networks (24, 28) to adaptively modify, based on historical process data (32), parameters provided to the respective fabrication steps. The analysis subsystem may include a electromagnetic source (61), a detector (66), a processor (67), a controller (68) and a scanning actuator (65).

Abstract: Devices having voids are producible by employing an electrochemical corrosion process. For example, an electrically conductive region is formed to have a surrounding chemically distinct region. Such formation is possible through conventional semiconductor processing techniques such as a copper damascene process. The surrounded conducting material is configured to be in electrical communication with a charge separation structure. The electrically conducting region is contacted with a fluid electrolyte and electromagnetic radiation is made to illuminate the charge separation region to induce separation of electrons and holes. The resulting separated charges are used to drive an electrochemical corrosion process at the conductive material/electrolyte interface resulting in the removal of at least a portion of the electrically conducting material.

Abstract: A method includes detecting a person located between a projector and a surface on which a first image is projected by the projector, and automatically blacking out a portion of the first image, so that light from the projector does not fall on the face of the person.

Abstract: The invention, in one aspect, provides a semiconductor device (100), including transistors (105), dielectric layers (115, 120) located over the transistors (105), interconnects (122) formed within the dielectric layers (115, 120), and a test structure (130) located adjacent a hot-spot (125) of the semiconductor device (100) and configured to monitor a real-time operational parameter of at least one of the transistors (105) or interconnects (122).

Abstract: In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.

Abstract: Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.

Abstract: Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.

Abstract: Methods and apparatus for use with an integrated circuit device of a processing device of a network node of a digital networking system, configured to monitor one or more control messages received at the processing device from each of a plurality of CPE devices, and limiting the one or more control messages to one or more specified rates for a specified duration. The integrated circuit device is further configured to provide one or more data channels to the plurality of CPE devices from the processing device in response to the one or more control messages processed at the processing device.

Abstract: A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.

Abstract: Electrical devices having tunable capacitance are provided. The tunable capacitance is achieved by placing an appropriate material between substrate layers and by controllably applying a pressure to the material to compress the material or alter the shape of a well in which the material is contained, and thereby alter the capacitance of the electrical device. The composition, shape and dimension of the embedded materials determine how the capacitance of the electrical device is altered upon compression of the embedded material in response to an applied control signal. Generally, as the embedded material is compressed, the material will become more dense and the capacitance of the integrated electrical device is altered.

Abstract: Various embodiments of the present invention provide systems and methods for reduced latency feedback in a data processing system. For example, some embodiments provide a data processing system that includes a variable gain amplifier, a processing circuit, a data detector, and an error signal calculation circuit. The variable gain amplifier amplifies a data input signal and provides an amplified signal. The processing circuit generates a signal output corresponding to the amplified signal, and includes a conditional multiplication circuit. The conditional multiplication circuit conditionally multiplies the signal output by a gain correction signal and provides the result as an interim output. The data detector applies a data detection algorithm to the signal output and provides an ideal output. The error signal calculation circuit generates a gain correction signal based at least in part on the interim output and a derivative of the ideal output.

Abstract: The invention provides a monolithic, highly integrated power supply circuit capable of providing various voltages for circuits on an expansion card, either from a main supply source or an auxiliary supply source. The monolithic power supply circuit preferably includes two switching converters, two low-drop-out regulators, a standby regulator, a reset circuit, and a control circuit. An associated method for providing various voltages via a monolithic power supply circuit is also disclosed.

Abstract: A semiconductor device package comprises a container having a base and side walls of an electrically insulating material. A semiconductor device chip is disposed on the base, and a lead frame extends through the side walls. At least one electrical conductor couples the lead frame to the chip. A first layer of an electrically insulating cured gel covers the chip and the lead frame, and a second layer of an electrically insulating cured gel covers at least the portion of the first layer that covers the chip, but does not extend to the side walls. In one embodiment, the second layer has the shape of a dome. In a preferred embodiment the gel comprises silicone. In another embodiment a third layer of conformal insulating material is disposed on the second layer and essentially fills the container. Also is described is a method of making the package for use with RFLDMOS chips.

Abstract: Various embodiments of the present invention provide systems and methods for storage medium flaw detection. For example, some embodiments provide flaw detection systems that include an input circuit, a data processing circuit and a defect detection circuit. The input circuit is operable to receive an input signal and to provide a filtered output. The data processing circuit is operable to receive the filtered output and to compute a difference between the filtered output and an expected output, and the defect detection circuit receives the difference between the filtered output and the expected output and compares a derivative of the difference with a threshold value, and asserts a defect signal when a magnitude of the derivative of the difference exceeds a threshold value.