Patents Assigned to Agere Systems
  • Method of manufacturing a laterally diffused metal oxide semiconductor device
    Patent number: 7927939
    Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventor: Charles W. Pearce
  • Methods and apparatus for improved phase switching and linearity in an analog phase interpolator
    Patent number: 7928789
    Abstract: Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: Ronald L. Freyman, Craig B. Ziemer
  • Systems and methods for LDPC decoding with post processing
    Patent number: 7930621
    Abstract: Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a method for post processing error correction in a decoder system is disclosed. The method includes receiving and iteratively decoding a soft input to generate a hard output associated with the soft input. The method further includes post processing when a plurality of parity checks fail. At least one bit of the hard output is identified as being potentially incorrect. The identified bit is modified, and the plurality of parity checks is thereafter repeated.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventor: Hao Zhong
  • Methods and apparatus for updating data structures during in-service upgrade of software in network processor
    Patent number: 7930691
    Abstract: Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of managing data structures associated with code executable on a packet processor includes the following steps. Data structures in the code are identified as being one of static data structures and non-static data structures, wherein a static data structure includes a data structure that is not changed during execution of the packet processor code and a non-static data structure includes a data structure that is changed during execution of the packet processor code. One or more data structures associated with the packet processor code are managed in a manner specific to the identification of the one or more data structures as static data structures or non-static data structures. At least a portion of the data structures may include tree structures.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: Rajarshi Bhattacharya, David P. Sonnier, Narender Reddy Vangati
  • Method of manufacturing a laterally diffused metal oxide semiconductor device
    Patent number: 7927940
    Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventor: Charles W. Pearce
  • Modifying integrated circuit designs to achieve multiple operating frequency targets
    Patent number: 7930674
    Abstract: A first integrated circuit design with a first maximum operating frequency is modified to achieve a second integrated circuit design with a second maximum operating frequency. The integrated circuit design comprises an arrangement of cells. Each of these cells drives a signal that propagates through a net of other circuit elements to one or more nodes that are limited by respective signal timing constraints. An analytical cost function is assigned to each of the cells. Each analytical cost function comprises a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design. One or more of the cells are replaced with different cells based on the determined analytical cost functions.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: James C. Parker, Vishwas Rao
  • Memory device with error correction capability and preemptive partial word write operation
    Patent number: 7930615
    Abstract: A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
  • Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow
    Patent number: 7923340
    Abstract: The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: April 12, 2011
    Assignee: Agere Systems Inc.
    Inventors: Alan S. Chen, Mark Dyson, Nace M. Rossi, Ranbir Singh, Xiaojun Yuan
  • Method and apparatus for adjusting a power supply of an integrated circuit
    Patent number: 7923868
    Abstract: Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: April 12, 2011
    Assignee: Agere Systems Inc.
    Inventors: Joseph Anidjar, Mohammad S. Mobin, Gregory W. Sheets, Vladimir Sindalovsky, Lane A. Smith
  • Controlling warping in integrated circuit devices
    Patent number: 7923347
    Abstract: Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: April 12, 2011
    Assignee: Agere Systems, Inc.
    Inventors: John W. Osenbach, Thomas H. Shilling, Weidong Xie
  • Systems and methods for tri-column code based error reduction
    Patent number: 7925959
    Abstract: Various systems and methods for tri-column code based error reduction are disclosed herein. For example, a digital information system is disclosed that includes channel detector. Such a channel detector receives an encoded data set and provides an output representing the encoded data set. The exemplary system further includes a decoder that receives the first output and is operable to perform three slope parity checks on the received first output. In turn, the decoder provides another output representing the encoded data set.
    Type: Grant
    Filed: July 10, 2010
    Date of Patent: April 12, 2011
    Assignee: Agere Systems Inc.
    Inventor: Weijun Tan
  • Remote control code filtering used for relaying of remote control codes
    Patent number: 7924167
    Abstract: Remote control code filtering techniques are disclosed that are suitable for use in a remote control code relaying system. A portion of a received remote control code is compared with corresponding portions of stored remote control codes. The received remote control code can be filtered based on the comparison. The filtering can comprise outputting the received remote control code or a portion thereof, discarding the received remote control code, or adding a new remote control code to the stored remote control codes. The remote control code can be received from a network or from a hardware interface (e.g., which converts an electromagnetic remote control signal to the remote control code). The received remote control code can be output to a network or to a hardware interface for subsequent transmission of an electromagnetic remote control signal. Filtering can occur before or after the network.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: April 12, 2011
    Assignee: Agere Systems Inc.
    Inventors: Piet Bernard Hesdahl, Amiram Levi
  • Methods and apparatus for reorganizing cells buffered after transmission
    Patent number: 7924857
    Abstract: A method and apparatus of reorganizing cells received over data communication lines at a receive node is provided. The cells have an initial order identified by monotonically increasing sequence identifiers. The receive node has buffers associated with respective ones of the communication lines. Each of the buffers has an output position. A cell having a smallest sequence identifier is detected from one or more cells at the output positions of the buffers. It is determined if the smallest sequence identifier is sequentially consecutive to a specified sequence identifier. If the smallest sequence identifier is sequentially consecutive to the specified sequence identifier, the cell having the smallest sequence identifier is dequeued from an output position of one of the buffers and the specified sequence identifier is redefined as the smallest sequence identifier.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: April 12, 2011
    Assignee: Agere Systems Inc.
    Inventors: Deepak Kataria, Codrut Radu Radulescu
  • Differential flash memory programming technique
    Patent number: 7920425
    Abstract: The invention relates flash memory programming techniques. An object of the invention is to provide a flash memory programming technique avoiding problems of the known state of the art and in particular, saving a significant amount of time during the development and/or production phases of any equipment containing flash memory devices and also saving time during an updating or upgrading procedure of such an equipment already being in use. Accordingly, the invention proposes for programming a flash memory device to program only differences in information between data already stored in the flash memory device and new data to be stored.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: April 5, 2011
    Assignee: Agere Systems Inc.
    Inventors: Martin A. Lohse, Kenneth A. Tuchman
  • Method and apparatus for adjusting the cadence of music on a personal audio device
    Patent number: 7915512
    Abstract: Disclosed is an audio device that adjusts the cadence of played songs. A user sensor determines cadence data based on movement of the user. A desired cadence is determined based on the cadence data received from the sensor. The cadence of songs is determined by low pass filtering digital representations of the songs and determining the period (T) of the back beat of the songs. An adjustment of the period (T) of the songs is then determined such that the adjustment of the period (T) of the songs results in the songs having the desired cadence. The period (T) of the back beat of the subsequent songs are then adjusted.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: March 29, 2011
    Assignee: Agere Systems, Inc.
    Inventors: Roger A. Fratti, Cathy Lynn Hollien, Arlen R. Martin
  • Method and apparatus for reducing latency in a clock and data recovery (CDR) circuit
    Patent number: 7916822
    Abstract: Disclosed is a system and method for a clock and data recovery (CDR) circuit. A phase selection circuit (PSC) generates a signal comprising frequency and phase. A voltage controlled oscillator (VCO) connected to the PSC generates a clock signal. The clock signal controls the frequency of the signal. The CDR circuit also includes a phase adjustment signal generator connected to the PSC for generating a phase adjustment signal. The phase adjustment signal controls the phase of the signal.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: March 29, 2011
    Assignee: Agere Systems Inc.
    Inventors: Pervez M. Aziz, Gregory W. Sheets
  • Method and system for monitoring a telecommunications signal transmission link
    Patent number: 7917657
    Abstract: A system including an event monitor for monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to a centralized storage register. The address sequencer also transmits the addresses to the storage register. The event monitor compares new event data for each address with old event data stored by the event monitor. If a difference is detected, the event monitor sends a strobe signal to the storage register, which stores the event data reflecting the difference and the related address data. The strobe signal is also sent to a signaling device, which sends an interrupt signal to cause a microprocessor to read the event and address data from the storage register. Optionally, the signaling device does not send an interrupt signal until a threshold number of strobe signals have been received.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: March 29, 2011
    Assignee: Agere Systems Inc.
    Inventor: Geoffrey D. Lloyd
  • Virtual segmentation system and method of operation thereof
    Patent number: 7912069
    Abstract: A virtual segmentation system and a method of operating the same. In one embodiment, the virtual segmentation system includes a protocol data unit receiver subsystem configured to (i) receive at least a portion of a protocol data unit and (ii) store the at least a portion of the protocol data unit in at least one block, and a virtual segmentation subsystem, associated with the protocol data unit receiver subsystem, configured to perform virtual segmentation on the protocol data unit by segmenting the at least one block when retrieved without reassembling an entirety of the protocol data unit.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: March 22, 2011
    Assignee: Agere Systems Inc.
    Inventors: David B. Kramer, David P. Sonnier
  • Reducing false detection in an HSDPA 3G terminal
    Patent number: 7912028
    Abstract: In one embodiment, a method for determining whether an encoded message in a shared channel is not intended for a communications device. The method includes: (a) decoding the message to recover a multi-bit codeword; (b) determining whether the codeword is valid or invalid, wherein, if the codeword is determined to be invalid, then the encoded message is not intended for the communications device; and (c) if the codeword is determined to be valid, then performing one or more other steps of the method to determine whether the encoded message in the shared channel is not intended for the communications device.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: March 22, 2011
    Assignee: Agere Systems Inc.
    Inventors: Eliahou Arviv, Rafael Carmon, Simon Issakov
  • Inductive coupling for communications equipment interface circuitry
    Patent number: 7912210
    Abstract: A system for improving the attenuation of an undesired signal found in a differential signal path through the use of inductive coupling. The system includes a primary inductor, a secondary inductor, and a filter. The primary inductor and the secondary inductor operably couple an input differential signal pair to an output differential signal pair, and the filter attenuates an undesired signal in the output differential signal pair.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: March 22, 2011
    Assignee: Agere Systems Inc.
    Inventors: Timothy W. Fuehrer, Donald R. Laturell, Lane A. Smith, Christopher J. Wittensoldner