Patents Assigned to Agere Systems
  • Software based thermal charging regulation loop
    Patent number: 7944180
    Abstract: The present invention implements a software controlled thermal feedback system for battery charging circuitry in portable devices, specifically in cellular telephones. The charging hardware block is integrated into a mixed-signal analog base-band (ABB) circuit. In addition to standard function controls, integrated within the ABB are silicon temperature sensors used to monitor the temperature of any silicon components integrated on the ABB and detect any temperature change due to thermal heating. The temperature value is passed to the digital base band (DBB) circuit. Here, a microcontroller is programmed to perform power management functions relating to the ABB. Thermal control software, implemented on the DBB microcontroller, monitors the silicon temperature of the ABB and adjusts the power levels on the ABB accordingly to provide a controlled chip temperature.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: May 17, 2011
    Assignee: Agere Systems Inc.
    Inventor: Douglas D. Lopata
  • Methods and appratus for evaluating a utilization of a system that provides connections using a normalized bandwidth scheme
    Patent number: 7944830
    Abstract: Methods and apparatus are provided for evaluating the throughput limit of a communication system, such as a network node or system. A throughput limit of a communication system is evaluated by receiving a request to allocate at least one connection of a given data type; obtaining an assigned weight for the at least one connection, wherein the assigned weight is based on the throughput limit and a processing limit indicating a throughput of the communication system for the given data type within a given time window; and determining whether to allocate the at least one connection of a given data type based on whether a sum of the assigned weights for each existing allocated connection for each data type exceeds the throughput limit. The assigned weight for a given data type can be subtracted from the sum upon receiving a request to de-allocate a connection.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: May 17, 2011
    Assignee: Agere Systems Inc.
    Inventors: Michael S. Shaffer, Jay P. Wilshire, Harold J. Wilson
  • BUFFER-BASED GENERATION OF OVSF CODE SEQUENCES
    Publication number: 20110110399
    Abstract: In one embodiment, a buffer-based method for generating codes (such as Orthogonal Variable Spreading Factor (OVSF) codes) for spreading and despreading data, without using a chip-rate counter. First, a buffer is populated with initial values based on a received spreading factor and desired code index. Next, a timing strobe is received, and the values in the buffer are changed upon receipt of the timing strobe based on an algorithm that is independent of any count value associated with the timing strobe. Finally, a code sequence value is generated based on the values in the buffer.
    Type: Application
    Filed: January 19, 2011
    Publication date: May 12, 2011
    Applicant: Agere Systems
    Inventors: Tomasz Prokop, Gongyu Zhou
  • Mobile telephone-based system and method for automated data input
    Patent number: 7941125
    Abstract: A system for, and method of automated data input that employs a mobile telephone as an input device. In one embodiment, the system includes: (1) a mobile telephone having a camera configured to generate an image of a document that contains the data, (2) a processing server adapted to receive the document via a wireless communication network, extract the data from the image and arrange the data according to a format and (3) a database, associated with the interpreter, that receives and stores the data according to the format.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: May 10, 2011
    Assignee: Agere Systems, Inc.
    Inventors: Michael J. Chambers, Michael Kiessling
  • Cue-based audio coding/decoding
    Patent number: 7941320
    Abstract: Generic and specific C-to-E binaural cue coding (BCC) schemes are described, including those in which one or more of the input channels are transmitted as unmodified channels that are not downmixed at the BCC encoder and not upmixed at the BCC decoder. The specific BCC schemes described include 5-to-2, 6-to-5, 7-to-5, 6.1-to-5.1, 7.1-to-5.1, and 6.2-to-5.1, where “0.1” indicates a single low-frequency effects (LFE) channel and “0.2” indicates two LFE channels.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: May 10, 2011
    Assignee: Agere Systems, Inc.
    Inventors: Frank Baumgarte, Jiashu Chen, Christof Faller
  • Communications system with symmetrical interfaces and associated methods
    Patent number: 7940808
    Abstract: A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: May 10, 2011
    Assignee: Agere Systems Inc.
    Inventors: Michael S. Shaffer, Himanshu Mahendra Thaker, Charles Albert Webb, III, Lesley Jen-Yuan Wu
  • Continuous power transfer scheme for two-wire serial link
    Patent number: 7940921
    Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: May 10, 2011
    Assignee: Agere Systems Inc.
    Inventors: Boris A. Bark, Peter Kiss, Johannes G. Ransijn, James D. Yoder
  • Method and apparatus for evaluating performance of a read channel
    Patent number: 7941732
    Abstract: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: May 10, 2011
    Assignee: Agere Systems Inc.
    Inventors: Nils Graef, Zachary Keirn
  • Method and apparatus for increasing yield in a memory device
    Patent number: 7940594
    Abstract: An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the subdivision. The electronic circuit further includes a controller including multiple outputs, each of the outputs being connected to a corresponding one of the voltage supply connections. When a given one of the subdivisions does not include a weak circuit element, the controller supplies a first voltage level to the given subdivision via the corresponding voltage supply connection. When the given subdivision includes at least one weak circuit element, the controller is operative to supply at least a second voltage level to the given subdivision via the corresponding voltage supply connection, the second voltage level being greater than the first voltage level.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: May 10, 2011
    Assignee: Agere Systems Inc.
    Inventors: Richard Bruce Dell, Ross A. Kohler, Richard J. McPartland, Hai Quang Pham, Wayne E. Werner
  • Reliability unit for determining a reliability value for at least one bit decision
    Patent number: 7937649
    Abstract: A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: May 3, 2011
    Assignee: Agere Systems Inc.
    Inventors: Jonathan James Ashley, Kelly Knudson Fitzpatrick, Erich Franz Haratsch
  • Memory device with reduced buffer current during power-down mode
    Patent number: 7933155
    Abstract: A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry. The control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device. The buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by the buffer in the power-down mode of operation. The buffer may comprise an input data buffer or an address buffer of the memory device.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: April 26, 2011
    Assignee: Agere Systems Inc.
    Inventors: Dennis E. Dudeck, Donald Albert Evans, Hai Quang Pham, Wayne E. Werner, Ronald James Wozniak
  • Methods and apparatus for updating data structures during in-service upgrade of software in network processor
    Patent number: 7930691
    Abstract: Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of managing data structures associated with code executable on a packet processor includes the following steps. Data structures in the code are identified as being one of static data structures and non-static data structures, wherein a static data structure includes a data structure that is not changed during execution of the packet processor code and a non-static data structure includes a data structure that is changed during execution of the packet processor code. One or more data structures associated with the packet processor code are managed in a manner specific to the identification of the one or more data structures as static data structures or non-static data structures. At least a portion of the data structures may include tree structures.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: Rajarshi Bhattacharya, David P. Sonnier, Narender Reddy Vangati
  • Method of transmitting data, a controller and a wireless communications device
    Patent number: 7929972
    Abstract: The present invention provides a method of transmitting data across a communications network having multiple channels, a controller for use with a transceiver in a wireless communications network and a wireless communications device. In one embodiment, the method of transmitting data includes establishing a bandwidth for transmission of the data based on a priority status thereof, selecting a modulation scheme and symbol rate as a function of the establishing the bandwidth, concluding if at least one channel from the multiple channels provides the bandwidth and transmitting the data over the as least one channel based on the concluding.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: John L. Blair, Ming-Ju Ho, Michael S. Rawles, Raymond R. Thomas
  • Memory device with error correction capability and preemptive partial word write operation
    Patent number: 7930615
    Abstract: A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
  • Systems and methods for LDPC decoding with post processing
    Patent number: 7930621
    Abstract: Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a method for post processing error correction in a decoder system is disclosed. The method includes receiving and iteratively decoding a soft input to generate a hard output associated with the soft input. The method further includes post processing when a plurality of parity checks fail. At least one bit of the hard output is identified as being potentially incorrect. The identified bit is modified, and the plurality of parity checks is thereafter repeated.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventor: Hao Zhong
  • Methods and apparatus for improved phase switching and linearity in an analog phase interpolator
    Patent number: 7928789
    Abstract: Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: Ronald L. Freyman, Craig B. Ziemer
  • Method of manufacturing a laterally diffused metal oxide semiconductor device
    Patent number: 7927940
    Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventor: Charles W. Pearce
  • Modifying integrated circuit designs to achieve multiple operating frequency targets
    Patent number: 7930674
    Abstract: A first integrated circuit design with a first maximum operating frequency is modified to achieve a second integrated circuit design with a second maximum operating frequency. The integrated circuit design comprises an arrangement of cells. Each of these cells drives a signal that propagates through a net of other circuit elements to one or more nodes that are limited by respective signal timing constraints. An analytical cost function is assigned to each of the cells. Each analytical cost function comprises a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design. One or more of the cells are replaced with different cells based on the determined analytical cost functions.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: James C. Parker, Vishwas Rao
  • Method of manufacturing a laterally diffused metal oxide semiconductor device
    Patent number: 7927939
    Abstract: A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventor: Charles W. Pearce
  • Modulated disk lock clock and methods for using such
    Patent number: 7929237
    Abstract: Various embodiments of the present invention provide systems and methods for controlling access to a magnetic storage medium. As one example, a method for controlling access to a storage medium is disclosed that includes calculating a point to point error amount, and generating a incremental error value based at least in part on the point to point error amount. The incremental error value is applied incrementally across a defined number of clock cycles.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: April 19, 2011
    Assignee: Agere Systems Inc.
    Inventors: Jeffrey P. Grundvig, Richard Rauschmayer