Abstract: A voltage-controlled oscillator (VCO) generates a clock signal in response to an input feedback signal by applying tuning to a control loop error signal related to the input feedback signal and generating the clock signal using a voltage ramp signal that is ground referenced. The VCO includes an input tuning circuit applying tuning to a difference signal to generate a tuned voltage signal, a comparator to compare the tuned voltage signal to the ground-based ramp signal, an one-shot circuit to generate an one-shot signal pulse in response to the ramp signal increasing to the tuned voltage signal. The one-shot signal pulse is the clock signal and is also used to reset the ramp signal. In some embodiments, the voltage-controlled oscillator of the present disclosure is incorporated in a current mode hysteretic modulator.

Abstract: A controller for a switching regulator includes an error amplifier configured to receive a feedback voltage indicative of the regulated output voltage and a reference voltage, and to generate an error signal indicative of the difference between the feedback voltage and the reference voltage; a loop calculator configured to generate an output signal in response to the error signal, the output signal being used by the switching regulator to generate the regulated output voltage having a voltage value related to the reference voltage; and an output voltage adjust circuit configured to receive a sense current signal indicative of a current flowing through the load and to generate a voltage adjust signal in response to the sense current signal, the voltage adjust signal being applied to generate the reference voltage relative to a predetermined set voltage.

Abstract: A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second low side FET, a first high side FET, a second high side FET, a first metal clip, a second metal clip, and a molding encapsulation. The semiconductor package further comprises an optional integrated circuit (IC) controller or an optional inductor. A method for fabricating a semiconductor package. The method comprises the steps of providing a lead frame; attaching a first low side FET, a second low side FET, a first high side FET, and a second high side FET to the lead frame; mounting a first metal clip and a second metal clip; forming a molding encapsulation; and applying a singulation process.

Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.

Abstract: A method comprises the steps of providing a semiconductor device wafer; forming a first plurality of alignment marks on a first side of the semiconductor device wafer; forming a first pattern of a first conductivity type; forming a second plurality of alignment marks on a second side of the semiconductor device wafer; forming a bonded wafer by bonding a carrier wafer to the semiconductor device wafer; forming a third plurality of alignment marks on a free side of the carrier wafer; applying a grinding process; forming a plurality of device structure members; removing the carrier wafer; applying an implanting process and an annealing process; applying a metallization process and applying a singulation process.

Abstract: A method, system and computer program product for improving inductor current ramp down times in a DC-to-DC converter having an inductor conductively coupled to a low side transistor on a first side and an or-ing transistor coupled to a second side, where the DC-to-DC converter is in a phase redundant power supply. The method comprises turning off the low side transistor and turning off the or-ing transistor in response to an unloading transient.

Abstract: A power MOSFET Rdson compensation device comprising analog circuitry receives an input signal proportional to a voltage drop across a power MOSFET, one or more base reference voltages, a voltage-dependent reference voltage, and a temperature-dependent reference voltage. The analog circuitry is configured to produce an output current corresponding to the input signal with compensation for voltage and temperature variation of a drain-source on resistance of the power MOSFET.

Abstract: The invention proposes a system and method for extending the maximum duty cycle of a step-down switching converter to nearly 100% while maintaining a constant switching frequency. The system includes a voltage mode or current mode step-down converter driven by a leading edge blanking (LEB) signal, which operates at the desired switching frequency. More particularly, the LEB signal is connected to a slope generator and/or a current sensing network. In each switching cycle, the LEB signal forces the slope signal and/or current sensing signal to reinitiate, thereby achieving a constant switching frequency and disassociating the switching frequency of the converter from the error voltage VCOMP. Corresponding methods for how to extend the maximum duty cycle of a step-down switching converter while maintaining a constant frequency are also disclosed.

Abstract: A ramp signal generator generates a slope compensated ramp signal with optimal slope compensation for a current mode control modulator. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator is implemented using a switched capacitor circuit with charge scaling to generate the ramp signal with optimal slope compensation built into the ramp signal.

Abstract: A transient voltage suppressor (TVS) device uses a punch-through silicon controlled rectifier (SCR) structure for the high-side steering diode and/or the low-side steering diode where the punch-through SCR structure realizes low capacitance at the protected node. In some embodiments, the breakdown voltage of the TVS device is tailored by connecting two or more forward biased diodes in series. The low capacitance TVS device can be configured for unidirectional or bidirectional applications. In some embodiments, the TVS device includes a MOS-triggered silicon controlled rectifier as the high-side steering diode. The breakdown voltage of the TVS device can be adjusted by adjusting the threshold voltage of the MOS transistor.

Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs, and a Schottky diode area including a plurality of Schottky diodes formed in the drift region having the superjunction structure. Each of the integrated Schottky diodes includes a Schottky contact between a lightly doped semiconductor layer and a metallic layer.

Abstract: An integrated device and a method for making said integrated device. The integrated device includes a plurality of planar MOSFETs that have a first contact region formed in a first source region of a plurality of source regions and a second contact region formed in a second source region of the plurality of source regions. The first and second contact regions have respective portions of the source region doped with the second conductivity type, and the first and second contact regions are separated by a JFET region, wherein the JFET region is longer in one planar dimension than the other and the first and second contact regions are separated by the longer planar dimension. The JFET region is bounded on at least one side corresponding to the longer planar dimension by a source region and a body region in conductive contact with at least one contact region.

Abstract: A charger comprises a housing, a first multi-layer printed circuit board (PCB), a second multi-layer PCB, and a third multi-layer PCB. The first PCB comprises at least a portion of a primary side circuit. The second PCB comprises at least a portion of a secondary side circuit. The third PCB is perpendicular to the first PCB and the second PCB. An isolation coupling element is disposed on the third PCB. The isolation coupling element comprises a multi-layer PCB. The first PCB comprises a high voltage (HV) semiconductor package. A surface of a die paddle of the HV semiconductor package is exposed from a molding encapsulation of the HV semiconductor package.

Abstract: A detection circuit for detecting an inductor current flowing through an inductor is provided. The inductor is coupled to a switch. The detection circuit includes a comparison circuit and a signal generating circuit. The comparison circuit, having a first node, is configured to compare a conduction time of a diode of the switch with a time threshold to provide a first voltage at the first node. The signal generating circuit, coupled to the first node, is configured to output a first detection signal according to the first voltage. The first detection signal indicates whether the inductor current flowing through the inductor reaches a first current threshold. A switching regulator comprises the detection circuit. A control method controls the switching regulator.

Abstract: A circuit for providing temperature compensation to a sense signal having a first temperature coefficient includes a temperature compensation circuit receiving a temperature sense signal indicative of a temperature associated with the sense signal where the temperature compensation circuit is digitally configurable by at least one digital signal to generate a compensating impedance signal having a second temperature coefficient. The compensating impedance signal provides an impedance value in response to the temperature sense signal. The compensating impedance signal is applied to modify the sense signal to provide a modified sense signal having substantially zero temperature coefficient over a first frequency range. The circuit further includes an amplifier circuit receiving the modified sense signal and generating an output signal indicative of the sense signal where the output signal has substantially zero temperature coefficient over the first frequency range.

Abstract: A controller for a multi-phase switching regulator includes an error amplifier configured to generate an error signal indicative of the difference between a feedback voltage and a reference voltage; a loop calculator configured to generate control signals in response to the error signal to drive the power stages; and a dynamic phase management control circuit configured to generate a power efficiency value in response to the input current, the input voltage, the output current, and the output voltage. The dynamic phase management control circuit generates a phase selection signal indicating a first number of power stages to be activated in response to the first current signal and the power efficiency value. The phase selection signal is provided to the loop calculator to activate the first number of power stages.

Abstract: A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.

Abstract: A semiconductor device comprising a substrate layer, an epitaxial layer, a dielectric layer, a first aluminum layer, a first titanium interlayer and a second aluminum layer. The first titanium interlayer is disposed between the first aluminum layer and the second aluminum layer. A process for fabricating a semiconductor device comprising the steps of: preparing a semiconductor wafer; depositing a first aluminum layer onto the semiconductor wafer; depositing a first titanium interlayer onto the first aluminum layer; depositing a second aluminum layer onto the first titanium interlayer; applying an etching process so that a plurality of trenches are formed so as to expose a plurality of top surfaces of a dielectric layer; and applying a singulation process so as to form a plurality of separated semiconductor devices.

Abstract: A power conversion system includes a bridge switch circuit. The bridge switch circuit includes a plurality of switch sub-circuits, each switch sub-circuit includes: a switch for controlling switching of the switch sub-circuit; and a control unit configured to perform the following control cycle: When the voltage between the switch and the cathode is less than the first voltage threshold and the switch sub-circuit is not charged, the control unit controls the switch to be turned on, and starts charging the switch sub-circuit. When the voltage between the switch and the cathode is greater than a second voltage threshold, the control unit controls the switch to be turned off. When the charging voltage of the control unit is greater than the third voltage threshold, the control unit stops charging the switch sub-circuit. The circuit structure is simple and the circuit energy loss of the bridge rectifier is reduced.

Abstract: A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.