Abstract: A semiconductor device comprising a substrate layer, an epitaxial layer, a dielectric layer, a first aluminum layer, a first titanium interlayer and a second aluminum layer. The first titanium interlayer is disposed between the first aluminum layer and the second aluminum layer. A process for fabricating a semiconductor device comprising the steps of: preparing a semiconductor wafer; depositing a first aluminum layer onto the semiconductor wafer; depositing a first titanium interlayer onto the first aluminum layer; depositing a second aluminum layer onto the first titanium interlayer; applying an etching process so that a plurality of trenches are formed so as to expose a plurality of top surfaces of a dielectric layer; and applying a singulation process so as to form a plurality of separated semiconductor devices.

Abstract: A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, a metal slug, a plurality of spacers, a plurality of leads and a molding encapsulation. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the plurality of spacers. A bottom surface of the metal slug is exposed from the molding encapsulation. A process for fabricating the IPM comprises preparing the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar, the plurality of leads, the metal slug and the plurality of spacers and applying a molding process to form the molding encapsulation.

Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.

Abstract: A constant on-time isolated converter comprises a transformer with a primary side and a secondary side. The primary side is connected to an electronic switch and secondary-side is connected to a load and a processor. The processor is connected to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal accordingly. The driver receives the control signal through the coupling element and accordingly changes the ON/OFF state of the electronic switch, regulating the output voltage and the output current via the transformer, where the duration of the ON/OFF state of the electronic switch is determined between the moment control signal changes from negative to positive and the moment it changes from positive to negative to achieve a high-speed load transient response.

Abstract: A semiconductor wafer is singulated to form a plurality of semiconductor packages. The semiconductor wafer has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A semiconductor package has a semiconductor substrate, a metal layer, an adhesive layer, a rigid supporting layer, a passivation layer and a plurality of contact pads. A thickness of the rigid supporting layer is larger than a thickness of the semiconductor substrate. A thickness of the metal layer is thinner than the thickness of the semiconductor substrate. An entirety of the rigid supporting layer may be made of a single crystal silicon material or a poly-crystal silicon material. The single crystal silicon material or the poly-crystal silicon material may be fabricated from a reclaimed silicon wafer. An advantage of using a reclaimed silicon wafer is for a cost reduction.

Abstract: An isolation coupling structure for transmitting a feedback signal between a secondary side and a primary side of a voltage conversion device includes a first dielectric layer including a first face and a second face opposite to the first face, a first coupling coil disposed on the first face enclosing to form an inner region; a second coupling coil configured to couple with the first coupling coil. The second coupling coil includes a first coil portion and a second coil portion, where the first coil portion is disposed on the second face, the second coil portion is disposed on the first face and located inside the inner region. The second coil portion is isolated from the first coupling coil, and the first coil portion and the second coil portion are electrically connected. The technical effect is that it can realize the electrical isolation and the coupling with low cost and small package size.

Abstract: A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.

Abstract: A power conversion system and a method for voltage change detection, specifically, relates to a detection circuit implemented in the AC-DC power converter, detect the voltage change. The AC input voltage is rectified to convert into a DC input voltage transmitted to a detection unit generating a detection voltage signal at different logical states corresponding to the input voltage changes. A charge current source unit is used for charging the capacitor when the detection voltage signal is in a second state and a discharge current source unit is used for discharging the capacitor when the detection voltage signal is in a first state. A primary comparator compares the voltage changes of the capacitor in the alternating charge and discharge processes with a critical zero potential and outputs a detection signal identifying the changing trend of the input voltage.

Abstract: A semiconductor device comprising a substrate layer, an epitaxial layer, a dielectric layer, a first aluminum layer, a first titanium interlayer and a second aluminum layer. The first titanium interlayer is disposed between the first aluminum layer and the second aluminum layer. A process for fabricating a semiconductor device comprising the steps of: preparing a semiconductor wafer; depositing a first aluminum layer onto the semiconductor wafer; depositing a first titanium interlayer onto the first aluminum layer; depositing a second aluminum layer onto the first titanium interlayer; applying an etching process so that a plurality of trenches are formed so as to expose a plurality of top surfaces of a dielectric layer; and applying a singulation process so as to form a plurality of separated semiconductor devices.

Abstract: A constant on-time isolated converter comprising a transformer is disclosed. The transformer primary side connects to an electronic switch and secondary-side connects to a load and a processor. The processor connects to a driver on primary side through at least one coupling element and to the electronic switch. The processor receives an output voltage or an output current across the load generating a control signal. The driver receives control signal through the coupling element and accordingly changes the electronic switch ON/OFF state, regulating output voltage and current via the transformer, where the electronic switch ON/OFF duration is determined between the moment control signal changes from negative to positive and the moment it changes from positive to negative to achieve a high-speed response to load transient.

Abstract: Aspects of the present disclosure disclose a superjunction trench MOSFET device for low voltage or medium voltage devices and a method of fabricating the same. The superjunction trench MOSFET device according to aspects of the present disclosure comprises an active cell region and a termination region disposed at an outer periphery of the active cell region. The active cell region comprises an array of device cells with the superjunction structure. The termination region may comprise a termination structure. In one embodiment, the termination structure includes guard rings in an intrinsic epitaxial layer. In one embodiment, the termination structure includes an array of floating P columns. In another embodiment, the termination structure includes an array of floating P columns and floating termination trenches.

Abstract: A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.

Abstract: Aspects of the present disclosure disclose a power semiconductor device coupled to a load operable to draw a load current comprising a power switch having a first terminal coupled to the load and a controller coupled to a control terminal of the power switch. The controller comprises a gate driving circuit configured to provide control of the control terminal of the power switch during normal switching operations; an overvoltage detection circuit configured to detect an overvoltage event occurring at the first terminal of the power switch; and an overvoltage protection circuit configured to provide control of the control terminal of the power switch during detection of the overvoltage event.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, a metal slug, a plurality of spacers, a plurality of leads and a molding encapsulation. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the plurality of spacers. A bottom surface of the metal slug is exposed from the molding encapsulation. A process for fabricating the IPM comprises preparing the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar, the plurality of leads, the metal slug and the plurality of spacers and applying a molding process to form the molding encapsulation.

Abstract: A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.

Abstract: A shielded gate trench field effect transistor comprises an epitaxial layer above a substrate, a body region, a trench formed in the body region and epitaxial layer and one or more source regions formed in a top surface of the body region and adjacent a sidewall of the trench. A shield electrode is formed in a lower portion of the trench and a gate electrode is formed in an upper portion of the trench above the shield electrode. The shield electrode is insulated from the epitaxial layer by a first dielectric layer. The gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer. The first and second dielectric layer has a same thickness.

Abstract: A voltage converter comprises a second controller as a power switch of the secondary side of the transformer for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage and generating a control signal, and a coupling element for transmitting the control signal generated by the second controller to the first controller on the primary side of the transformer enabling the first controller to generate a first pulse signal driving the power switch to control the on/off state of the primary side winding.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, an IC, a plurality of leads and a molding encapsulation. The first MOSFET is attached to the first die paddle. The second MOSFET is attached to the second die paddle. The third MOSFET is attached to the third die paddle. The fourth, fifth and sixth MOSFETs are attached to the fourth die paddle. The IC is attached to the tie bar. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the IC. The IPM is a small-outline package. It reduces system design time and improves reliability. The IC includes boost diodes. It reduces a package size of the IPM.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die supporting elements, a first, second, third, fourth, fifth and sixth transistors, a connection member, a low voltage IC, a high voltage IC, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die supporting element. The second transistor is attached to the second die supporting element. The third transistor is attached to the third die supporting element. The fourth, fifth and sixth transistor s are attached to the fourth die supporting element. The low and high voltage ICs are attached to the connection member. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first, second, third, fourth, fifth and sixth transistors, the connection member and the low and high voltage ICs. The IPM has a reduced thermal resistance of junction-to-case (RthJC) compared to a conventional IPM.