Abstract: Improved CO2 sorbents comprised of a mesoporous silica functionalized with a polyamine are obtained by the in-situ polymerization of azetidine. Also included herein are processes utilizing the improved CO2 sorbents wherein CO2 is chemisorbed onto the polyamine portion of the sorbent and the process is thermally reversible.

Abstract: An oxygen concentrator is for generating a flow of oxygen by electrolysis of atmospheric humidity. It comprises a cathode (24) and an anode (26) contacting opposite sides of a proton-conducting membrane (12). A catalytic apparatus (14) comprises a diffusion layer (28) which spaces a catalyst (30) from the cathode. The cathode and the catalytic apparatus are contained within a cathode chamber which comprises a ventilation means (44) for allowing a controlled flow of air to the catalyst. In operation water is electrolysed at the anode and hydrogen generated at the cathode flows through the diffusion layer to the catalyst, where it reacts with atmospheric oxygen to form water which flows back to the proton-conducting membrane for further electrolysis.

Abstract: Apparatus (1) for determining a property of a sample. The apparatus has a chamber (11, 13) for receiving at least a part of the sample and contains a rotor (15) adapted to rotate within the chamber (11, 13). The apparatus (1) also has a space (17) between the rotor (15) and the chamber (11, 13) which may be at least partially occupied by the sample, driving means (14) for rotating the rotor (15), and a detector (39) arranged to detect the rate of rotation of the rotor (15). The apparatus may also have two parts, a sample strip (5) for receiving the sample and a receiving member (3) for receiving the sample strip (5) and carrying out measurements on the sample. The rotor (15) may be magnetised across its diameter. The driving means (14) may be a magnetic driving means. The sample may be a blood sample. The property to be determined by the sample may be the prothrombin time of the blood or plasma.

Abstract: An assay apparatus having an assay strip. The assay strip has a first area with a plurality of magnetic particles bonded thereto. The assay strip also has a microfluidic (or nanofluidic) channel or chamber, having a sensing area including one or more magnetic particle traps and a magnetic field source provided adjacent to the sensing area. Introduction of a fluid causes the magnetic particles to become attached to or displaced by a substance of interest, travel along the microfluidic channel to the sensing area and become concentrated in the one or more traps thus providing an indication of the presence or absence of a substance of interest in the fluid. There may be a plurality of traps.

Abstract: Disclosed is a melt processible semicrystalline fluoropolymer comprising: (a) about 0.001 to about 25 weight percent of repeating units arising from a hydrocarbon monomer having a functional group and a polymerizable carbon-carbon double bond, wherein said functional group is at least one selected from the group consisting of amine, amide, hydroxyl, phosphonate, sulfonate, nitrile, boronate and epoxidehydrocarbon monomer; and (b) the remaining weight percent of repeating units arising from tetrafluoroethylene. This melt processible semicrystalline fluoropolymer is impermeable to fuels and is useful as a lining for petroleum fuel tubing, as well as chemical resistance coating for, or adhesive between, perfluoropolymer and other polymers, metals and inorganics.

Abstract: A medical data collection method and system (10) for gathering medical data from an individual when the individual is located remotely from a healthcare professional. A computer device that includes an aggregation device (22) is used at the patient remote site (11) for collecting medical data/information from various medical devices (14) that can gather appropriate medical data. The aggregation device (22) sends the recorded medical data using a Service Oriented Architecture (SOA) web service/application (25) to a network 16. The information may be saved on a local or centralized data storage device (18) and/or stored to a patient's medical record. A healthcare provider (i.e.

Abstract: Embodiments described herein provide a programmable mapping scheme for mapping information to resources of a system. In an embodiment, a programmable lattice method operates to map information to resources of a system. For example, the programmable lattice method can be used to map pixel data to graphics processing resources of a graphics processing system. In another embodiment, a programmable hybrid method operates to map information to resources of a system. For example, the programmable hybrid method can be used to map pixel data to graphics processing resources of a graphics processing system. The mapping methods described are applicable to any multi-dimensional array processing (e.g., 2D and 3D). The methods provide a uniform distribution of resources and tend to reduce resource collisions when allocating information to a resource.

Abstract: Method and apparatus of using a system memory for 3D comb filtering for PCTV application are provided. Firstly, the data reading/writing in a logic address may be controlled, and mapping the logic address to a physical address in the system memory, and actually reading/writing data in the physical address. A RSM and a WSM may be used to control reading/writing data in the logic address respectively, wherein the WSM switching among its idle status, request status, and processing status, and the RSM switches among its idle status, request status and waiting status. An address mapping table may be used to record the logic address and corresponding physical address. Upon obtaining the physical address via the address mapping table, actually reading/writing data in the physical address. Method and apparatus for adaptively controlling of 3D comb filter on/off depending on the status of the video decoder and on-chip memory.

Abstract: A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.

Abstract: Disclosed is an electrochemical etching system with localized etching capability. The system allows multiple different porous semiconductor regions to be formed on a single semiconductor wafer. Localized etching is achieved through the use of one or more stationary and/or movable computer-controlled inner containers operating within an outer container. The outer container holds the electrolyte solution and acts as an electrolyte supply source for the inner container(s). The inner container(s) limit the size of the etched region of the semiconductor wafer by confining the electric field. Additionally, the current amount passing through each inner container during the electrochemical etching process can be selectively adjusted to achieve a desired result within the etched region. Localized etching of sub-regions within each etched region can also be achieved through the use of different stationary and/or moveable electrode structures and shields within each inner container.

Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.

Abstract: A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.

Abstract: A method for forming a field effect transistor (FET) device includes forming a gate conductor and gate dielectric on an active device area of a semiconductor wafer, the semiconductor wafer including a buried insulator layer formed over a bulk substrate and a semiconductor-on-insulator layer initially formed over the buried insulator layer. Source and drain extensions are formed in the semiconductor-on-insulator layer, adjacent opposing sides of the gate conductor, and source and drain sidewall spacers are formed adjacent the gate conductor. Remaining portions of the semiconductor-on-insulator layer adjacent the sidewall spacers and are removed so as to expose portions of the buried insulator layer. The exposed portions of the buried insulator layer are removed so as to expose portions of the bulk substrate. A semiconductor layer is epitaxially grown on the exposed portions of the bulk substrate and the source and drain extensions, and source and drain implants are formed in the epitaxially grown layer.

Abstract: A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.

Abstract: A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.

Abstract: A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.

Abstract: A method of forming a semiconductor device including forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium, and the second deposit having a second percentage of germanium that is less than the first percentage and supports forming a silicide deposit on the second deposit. A structure is also provided.

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture.

Abstract: A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate, and a high-k dielectric layer (having a dielectric constant above 4.0) contacting (on) the interface layer. A Nitrogen rich first metal Nitride layer contacts (is on) the dielectric layer, and a metal rich second metal Nitride layer contacts (is on) the first metal Nitride layer. Finally, a Polysilicon cap contacts (is on) the second metal Nitride layer.

Abstract: A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.