Abstract: A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107).

Abstract: An improved rare probability connection call registration method which utilizes automatic congestion level (ACL) information within a release message for an asynchronous transfer mode (ATM) switching system. The method includes the steps of setting a predetermined threshold value, receiving a call releasing message, checking automatic congestion level (ACL) information in the call release message, and determining whether an ACL information is set. When the ACL information is not set continuous checks are made, and the method continues by increasing the count value when the ACL information is set, and it is determined whether the value of the ACL counter is greater than a predetermined threshold value.

Abstract: A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

Abstract: Multiple banks associated with a multiple set associative cache are stored in a single chip, reducing the number of SRAMs required. Certain status information for the second level (L2) cache is stored with the status information of the first level cache. This enhances the speed of operations by avoiding a status look-up and modification in the L2 cache during a write operation. In addition, the L2 cache tag address and status bits are stored in a portion of one bank of the L2 data RAMs, further reducing the number of SRAMs required. Finally, the present invention also provides local read-write storage for use by the processor by reserving a number of L2 cache lines.

Abstract: A dual-mode baseband controller enables a single integrated circuit to support either In-Phase Quadrature (I-Q) or Non-Return to Zero (NRZ) radio-frequency transmitter architectures for use in second generation (CT2) cordless telephones. A radio frequency (RF) interface circuit controls output signals to support either the I-Q architecture or the NRZ architecture, depending on a MODE control bit received from a controlling integrated circuit. The RF interface circuit comprises an I-Q waveform generator, four multiplexers, two digital-to-analog converters, a buffer, interconnecting circuitry, and a timing controller operating under configurable software control.

Abstract: A surface impedance measurement device comprises a transmitting antenna producing a magnetic field in the area surrounding a material to be tested and a receiving antenna receiving the magnetic field. An electric voltage wobbled in frequency is applied to the transmitting antenna, and a circuit measures the voltage at the terminals of the second antenna. For the antennae to be applied on the same side of the material to be tested and of which the surface impedance is to be measured, the antennae are superposed by the intermediary of a dielectric wedge in a compact probe. The impedance measurements are then independent of the dimensions and geometry of the material.

Abstract: The invention relates to a method and to a structural element for protecting an aircraft against the building-up, when flying, of electrostatic charges on the external metallic surface of the aircraft normally coated with a finishing dielectric paint.The structural element of the aircraft is subjected to a treatment consisting in applying on the external metallic surface of the aircraft, prior to the depositing of the finishing paint, a resistive electrostatic protection layer having a surface resistivity of between 1 and 100 M.OMEGA. per square and being connected to the reference electric potential (i.e., ground or mass) of the frame or body of the aircraft.The the protective layer is provided, for example, by applying at least a paint layer forming, once dry, a coating exhibiting the required surface resistivity.