Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.

Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.

Abstract: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.

Abstract: This disclosure describes use of dielectric islands embedded in metallized regions of a semiconductor device. The islands are formed in a cavity of a dielectric layer, as upright pillars attached at their base to an underlying dielectric. The islands break up the metal-dielectric interface and thus resist delamination of metal at this interface. The top of each island pillar is recessed from the cavity entrance by a selected vertical distance. This distance may be varied within certain ranges, to place the island tops in optimal positions below the top surface plane of the dielectric. Metallization introduced into the cavity containing the islands, submerges the island tops to at least a minimum distance to provide a needed minimum thickness of continuous metal. The continuous metal surface serves favorably as a last metal layer for attaching solder or for bump-bonding package to the IC; and also serves as an intermediate test or probe pad in an interior layer.

Abstract: Irradiation lamps of an ultraviolet-light irradiation apparatus are uniformly cooled to achieve an appropriate temperature of the walls of the lamps and the ultraviolet light emitted from the lamps is efficiently reflected toward an object to be irradiated so that the ultraviolet light is efficiently irradiated onto the object to be irradiated. A plurality of low-pressure mercury lamps are arranged in parallel. A reflective mirror is arranged above the low-pressure mercury lamps so as to reflect the ultraviolet light emitted by the low-pressure mercury lamps. An exhaust passage defined by the reflective mirror suctions air around the low-pressure mercury lamps and exhausts the suctioned air to outside. The reflective mirror has a plurality of openings arranged along a longitudinal direction of the low-pressure mercury lamps, and a part of the openings has a size different from a size of other parts of the openings.

Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.

Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming a first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below

Abstract: A scheme for graphical user interface using a polygonal-line-shaped slider that enables a user to intuitively manipulate-and playback spatio-temporal media data such as video data and animation data without deteriorating the temporal continuity of the data in interactive manipulation and playback of the spatio-temporal media data is disclosed. In this scheme, the slider is composed of a polygonal line composed of at least one segment and a coordinate indicator that is moved along the polygonal line. Data corresponding to coordinates specified by the coordinate indicator is entered. The apparatus according to present invention stores the coordinates of vertexes of the polygonal line, stores input coordinates, maps the input coordinates onto a point on the polygonal line, and positions the coordinate indicator at the point.

Abstract: A semiconductor device having reduced field oxide recess and method of fabrication is disclosed. The method of fabricating the semiconductor device begins by performing an HF dip process on a substrate after field oxidation followed by performing a select gate oxidation. Thereafter, a core implant and a field implant are performed. After the implants, a tunnel oxide mask is deposited. The select gate oxide is then etched in areas uncovered by the tunnel oxide mask, and tunnel oxidation is performed.

Abstract: The present invention provides for a method and an apparatus for archiving and retrieving data. At least one top-level directory is created to store files. A file-location database is created to track stored files in the top level directory. Files from a primary database are received. Files received from the database are archived into the top level directory, in response to receiving files from a primary database. An immediate backup of the archived files is created. A long-term backup of the archived files is created.

Abstract: The present invention provides for a method and an apparatus for performing automated rework in a manufacturing process. A lot of semiconductor devices is processed using a first set of control input parameters. The first set of control input parameters is stored in a memory location. Process data from the processing of the lot of semiconductor devices is acquired. Errors in the process data are analyzed. At least one automated rework procedure is performed on the lot of semiconductor devices in response to the analysis of the process data.

Abstract: A semiconductor device and a method of fabricating thereof, including an insulator layer having alternately layered insulator films and boundary layers, wherein the boundary layers are more dense than the insulator films to prevent expansion and elongation of string-like defects across the boundary layers. The method includes mixing a nitrogen containing gas and a silane group gas to form an insulator film; temporarily stopping a flow of the silane group gas for approximately one to fifteen seconds to form a boundary layer over the insulator film; restarting the flow of the silane group gas; and repeating the steps of temporarily stopping and restarting for a predetermined number of times to form the plurality of alternately layered insulator films and boundary layers. The plurality of alternately layered insulator films and boundary layers is also etched at an etching rate for the insulator films greater than an etching rate for the boundary layers to form a step-shaped sloped opening.

Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below t

Abstract: This invention relates to a method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of said device, wherein at least some of the contaminate nitrogen has formed a bond with the surface of the silicon substrate in contact with the gate oxide layer in said gate region, said method comprising: contacting said gate oxide layer and contaminate nitrogen with a gas comprising ozone at a temperature of about 850° C. to about 950° C. for an effective period of time to break said bond; and removing said gate oxide layer and contaminate nitrogen from said surface of said silicon substrate.

Abstract: Enhancement of attentional processing is attained by administration of an endorphinase inhibitor or enkephalinase inhibitor and optionally, a dopamine precursor, or a serotonin precursor, a GABA precursor, or an endorphin or enkephalinase releaser, or certain herbal compounds including Rhodiola rosea extract (Pharmaline) and/or Huperzine. These components promote restoration of normal neurotransmitter function and the components combined enhance the release of dopamine at the nucleus accumbens and are non-addictive. Use of the dopamine precursors L-phenylalanine, or L-Tyrosine, the enkephalinase inhibitor D-phenylalanine, and/or the serotonin precursor -hydroxytryptophan and a natural acetylcholenesterase inhibitor and chromium salts (i.e. picolinate, nicotinate, etc.) is especially preferred, but not limited to assist in relieving symptoms associated with brain phenylalanine deficiency.

Abstract: A method and apparatus for fabricating electrochemical copper interconnections between the component parts of an integrated circuit on a semiconductor device. A cathodic platter is provided that includes contact pins that contact the surface of a semiconductor wafer at predetermined locations during the electrochemical deposition process. The contact pins are arranged on the cathodic platter so that when placed on the surface of the semiconductor wafer the contact pins surround the perimetrical edges of each respective semiconductor device on the semiconductor wafer. Once the semiconductor wafer is properly positioned on the cathodic platter, a copper conductive layer can be electrochemically and uniformly deposited on the surface of the semiconductor device.

Abstract: A method is provided for fabricating a semiconductor device, the method including forming a first dielectric layer above a structure and forming an island of a sacrificial layer above the first dielectric layer. The method also includes introducing a first dopant into first portions of the structure, leaving a second portion of the structure protected by the island, and removing first portions of the island leaving a second portion of the island. The method further includes introducing a second dopant into the first portions and third portions of the structure, leaving a fourth portion of the structure protected by the second portion of the island. The method additionally includes forming a second dielectric layer adjacent the second portion of the island, removing the second portion of the island, forming a gate dielectric above the fourth portion of the structure and forming a gate conductor above the gate dielectric.

Abstract: A method of metallizing a semiconductor chip with copper including an inlaid low dielectric constant layer. The method includes the step of depositing a barrier layer on the surface of the semiconductor chip. Next, a copper seed layer is deposited on the barrier layer, and then the copper seed layer is annealed. Microlithography is then performed on the semiconductor chip to form a plurality of wiring line paths with a patterned photoresist layer. After the wiring line paths are formed a copper conductive layer is electroplated to the surface of the semiconductor chip. Next, the patterned photoresist layer is stripped off of the surface of the semiconductor chip. In addition, portions of the barrier layer and the copper seed layer that were covered by the patterned photoresist layer are also removed. A low dielectric constant layer is then deposited on the semiconductor chip to fill the gaps between the newly created copper conductive lines.

Abstract: A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107).

Abstract: An improved rare probability connection call registration method which utilizes automatic congestion level (ACL) information within a release message for an asynchronous transfer mode (ATM) switching system. The method includes the steps of setting a predetermined threshold value, receiving a call releasing message, checking automatic congestion level (ACL) information in the call release message, and determining whether an ACL information is set. When the ACL information is not set continuous checks are made, and the method continues by increasing the count value when the ACL information is set, and it is determined whether the value of the ACL counter is greater than a predetermined threshold value.