Abstract: A bypass means is provided for bypassing a system clock disabling signal around a conventional system clock disabling signal processing path to reduce the amount of delay between the occurrence of the disabling signal and a stopping of the system clock.

Abstract: A file system for managing data files for access by a plurality of users of a data processing system that includes internal storage for buffering, external storage, and a file user interface by which the plurality of users request access to data files. A first level, coupled to the file user interface in the internal storage allocates the internal storage for temporary storage of data to be accessed by the plurality of users, and generates requests for transactions with external storage in support of such allocations. A second level is coupled to the first level and the external storage and responds to the request for transactions with the external storage for managing the transactions for storage of data to, and retrieval of data from, the external storage. The second level defines a plurality of physical storage classes which are characterized by pre-specified parameters that allocate data files subject of transactions to locations in external memory.

Abstract: A data integrity system comprising a plurality of units connected together for the transfer of data between the units. Each said unit comprises data means for receiving data from one or more other units and/or transmitting data to one or more other units, first means, if the unit transmits data to other units, for generating a PARITY OUT signal indicating the parity of all data transmitted to the other units and second means, if the unit is to receive data from other units, for generating a PARITY IN signal indicating the parity of all data being received by the unit from the other units. A third means, located in one of said plurality of units, receives all the PARITY OUT signals and all the PARITY IN signals generated by the plurality of units and detects from all the received PARITY IN signals and all the PARITY OUT signals whether an error had occurred during the transfer of data between the units.

Abstract: A distributed computing system having a distributed protocol stack. In a system including one or more general purpose computers or other application processors for running applications, the distributed protocol stack off-loads communication or other I/O processing from the application processor to dedicated I/O processors using a STREAMS environment thereby enhancing the performance/capacity of the system. The distributed protocol stack is formed of a STREAMS stack top and a stack bottom so that together the stack top and stack bottom comprise a full stack functionally equivalent to a non-distributed stack running on an application processor. Both the application processors and the I/O processors together appear to execute the full protocol stack, but the application processor only executes the stack top while the I/O processor only executes the stack bottom.

Abstract: A clock distribution system for reducing clock skew between tightly coupled central processing units in a multi-processor system. The multi-processor system includes (1) a configuration processor for generating a first configuration signal and a second configuration signal, a first clock, a second clock, (2) a first processor having a first central processing unit, (3) a second processor having a second central processing unit, (4) a first clock generator for generating a first delayed clock signal from the first or second clock in accordance with the configuration signals, and (6) a second clock generator generating a second delayed clock signal from the first or second clock in accordance with said configuration signals.

Abstract: A SYStem COMmunication interface (SYSCOM) unit provides uniform communication between hardware and software units of a computer system. The computer units include Central Processing Units (CPU's), Input/Output Processors (IOP's), Service Processor (SVP), and Control State Software (CSSW) which runs on the CPU's operating in Control State. The SYSCOM communication interface includes signalling hardware, control blocks in storage, and a uniform communication method used for communication between the computer units. The communication method sends messages between an originating unit (ORG.U) and one or more destination unit(s) [DES.U(s)].

Abstract: The invention provides a method and apparatus for tagging a control error indication onto a data signal passing through a data router in a computer system.

Abstract: A pipelined computer which process operand data through a sequence of D,A,T,B,X and W stages includes a sidetrack queue. Data which exits the B stage prematurely, before the X stage is ready to immediately process such data, is held over in the sidetrack queue and presented to the X stage at a later time. The sidetracking mechanism is used to speed processing of rate-variable operand-consuming instructions such as the EDIT and EDMK commands.

Abstract: An interface between a storage unit and a system control unit maintains a sequential processing when retrying linestores by providing a single piece of information that the linestore is a "first" in a series. An initial request flag accompanies linestore requests to the system controller and is returned to the storage unit with linestore replies. A mode indicator coupled with the storage unit pipeline sets a retry mode latch in response to a linestore restart reply, and resets the retry mode latch in response to a linestore read reply by the system controller to an initial request. Logic in the pipeline suppresses requests for the system resource in the pipeline, other than initial requests, when the retry mode latch is set, such as by flagging data subject of the second flow as locked or otherwise invalid. The port includes a state machine which preserves the order of pending requests for the system resource.

Abstract: To perform a sort of N records, a two-dimensional tree structure is formed with a tree of subtrees, where each subtree is formed by a plurality of nodes organized in a binary tree. For each leaf node in the tree, there is an ancestor chain of nodes (from child to parent, from parent to grand-parent, from grand-parent to great-grand-parent, . . . and so on) that connects each leaf node to the root node. To perform the sort, the processing unit stores codes representing keys into nodes in the two-dimensional tree and performs a tree sort of the keys using the codes. The codes are accessed in the subtrees and processed to determine the sort order of the keys and therefore the sort order of the corresponding records.

Abstract: In a computer system including an interrupt processor for interrupting a program being processed by the computer system, a sub-system for processing interrupt requests to the interrupt processor. The sub-system comprises hardware circuit for generating hardware interrupt requests and control circuit for implementing control software where the control software causing software interrupt requests to be generated by said control circuit. An interrupt register stores and identifies both the hardware and software interrupt requests. A selection circuit selects and sends one of said stored interrupt request stored in the interrupt register to the interrupt processor for processing. The control circuit, under control of the control software, generates an end software interrupt requests for removing software interrupt request stored in the interrupt register such that software interrupt in the computer system can be generated and terminated under the control of the control software.

Abstract: The invention provides a method and apparatus for immediate control communications between supervising and main processor units.

Abstract: An apparatus and method for forcing stuck-at and transient errors at sequential and combinational logic and signal lines in a large scale data processing system. Error forcing is achieved by including a scan-in gate with error input and address lines for each scan point to be tested. A fault signal of adjustable duration is generated and combined in a unique fashion to an existing scan-in signal to permit either stuck-at or transient errors to be forced.

Abstract: An approach to error assessment in computer systems is based on storing important state information while the machine is operating in a trace memory for each cycle of the clock. The trace memory is then coupled through the scan interface or otherwise to the service processor for use in analyzing the error. A set of signal lines in the data processing system is connected in parallel to the input port of the trace memory. Storing logic is coupled to the processor clock and to the input port of the memory, for storing information from the set of signal lines in successive locations in the trace memory in response to successive cycles of the clock. The output port of the trace memory is coupled to the service processor. The system also includes logic which counts the number of cycles of the clock after detection of an error until stopping of the clock and a system for tagging storage locations in the trace memory that correspond to cycles in which an error was detected.

Abstract: A processing system comprising a first means for generating first signals indicating when the next instruction can begin processing where eight or less bytes are processed by the MOVE, PACK or UNPACK instruction, a second means for generating second signals if an overlap condition exists for the MOVE, PACK or UNPACK instruction being processed, and where the first means generates the first signals prior to the second means generating the second signals and independent of whether the second means generates the second signals.

Abstract: An error handling and reporting mechanism is capable of taking advantage of sophisticated error analysis performed after clocks have been stopped in response to an error detected in a controller. The controller provides services in a data processing system in response to requests for controller services from a plurality of requestors. The controller includes a plurality of ports for storing requests for controller services. A plurality of servers is coupled to the plurality of ports, and perform separate services associated with the requests for controller services stored in the plurality of ports. An error reporting mechanism is included which is responsive to a detected error in a particular server associated with a request in a particular port, for posting error status in the particular port and causing clock stoppage within a clock stop latency period. An error analysis mechanism analyzes the detected errors during the clock stoppage.

Abstract: An error detection scan tree apparatus and method including a plurality of error detection devices in which an error signal generated by an error detection device is propagated from the detection device through the scan tree of minimalistic structure to an error servicing unit. A plurality of scan out points are provided at specific locations within the scan tree that are capable of non-disruptively latching an error signal propagating therethrough so as to facilitate a more efficient scan out of the state of the system upon the occurrence of an error.

Abstract: A cache memory system includes a buffer having a plurality of segments storing lines of data in addressable storage locations. A first access path is used for accessing the plurality of segments in parallel for access by the CPU, and a second access path is provided for access to the plurality of segments in the buffer in parallel for cache consistency access. Access to damaged segments is selectively disabled by inhibiting tag match and line replacement through the first access path without affecting the second access path. Thus, by disabling the first access path to selected segments, a damaged segment is reconfigured offline without a quiescent state or an extended clocks off period affecting CPU performance.

Abstract: A mapping system for mapping a plurality of two byte operation code series into a control store where in each two byte operation code the first byte identifies the series in which that two byte operation code is included and the second byte identifies that specific operation code within the identified series, the mapping system comprising a first register for storing the first and second bytes of a two byte operation codes, a first control store for storing control word for the two byte operation codes, a first means for generating, from the first and second bytes stored in the first register, a first control store address for the first control store thereby providing access to the control word for processing the two byte operation code store in the first register and a second means for generating, from the first and second bytes stored in the first register, a first signal when an invalid two byte operation code has been stored in the first register for processing, the first signal invalidating the processin

Abstract: The invention provides a method and apparatus for logging all references to microstore addresses irrespective of the number of times that a same address is referenced and irrespective of the order in which addresses are referenced. It provides a log indicating simply whether each address of the microstore has or has not been referenced within a prescribed time period. There is no limit placed on the duration of the prescribed time period and thus logging can cover long-term events such as, the full execution of a single macro-instruction, the full execution of an assembly level routine or the execution of all micro-instructions resident in the microstore as they are subjected to all possible input parameters. A practical tool for global visualization of computer operations is therefore provided.