Abstract: An error recovery system used in a pipeline architecture type computer system for recovering from an error in a control word for an instruction without interrupting the sequence of processing control words by the computer system. The computer system processes instructions in a sequence of overlapping FLOWs where each FLOW is comprised of a sequence of cycles. An instruction control word is processed in each cycle of each FLOW. The error recovery system comprises a first storage for storing, for a given cycle of a FLOW, all the control words for all the instructions, a second storage for storing a control word read from the first storage and an error recovery logic for detecting an error in the control word read from the first storage and stored in the second storage and for correcting the error in the control word in the first and second storage.

Abstract: A selectable timing delay system which provides for delaying an input signal a specified length of time within a specified tolerance wherein the range and resolution of the selectable timing delay system are so specified that the selected delay within the selected tolerance is obtainable regardless of the relative speed of the integrated circuit chips used in forming the selectable timing delay system.

Abstract: A method and apparatus for locating the source of first error in a high speed synchronous system having a plurality of potential sources for first error is disclosed. An error-report collecting cell is provided having a plurality of self-freezing error history latches each including an output coupled to an report-condensing OR gate and a first-error code storing register. The report-condensing OR gate freezes a code value stored in the code register upon receipt of a first error report. The frozen code identifies the source of the first received error report. The report-condensing OR gate further initiates a clock counter upon receipt of the first error report. When system clocks stop, the contents of the clock counter indicate the number of clocks occurring between stoppage and receipt of the first error report by the cell. An error communication network is formed comprising a plurality of the above-described cells each receiving an error report either directly from an error detector or from another cell.

Abstract: A partitionable computing system includes main storage units on respective sides of the complex which can be fully controlled and accessible from either side. The system includes a dual port main storage unit design, and a system controller design capable of driving plural main storage unit interfaces. With this configuration, one system controller and the processors attached to that system controller can be taken offline and partitioned off to perform maintenance while all of the physical main storage units remain accessible to the processors on the surviving side of the complex. The operating system sees no loss available memory and the time to perform the maintenance activity is significantly reduced.

Abstract: A trace system for selectively storing in tags stored in a TAG IN register and out tags stored in a TAG OUT register of an I/O channel controlled by an I/O channel controller, the trace system comprising a first means for generating a first signal whenever an in tag is changed in the TAG IN register, a second means for generating a second signal whenever out tags are written into the TAG OUT register, a storage means for storing the in tags and the out tags and a control means for storing, in response to a first or second signal, the in tags stored in the TAG IN register and the out tags stored in the TAG OUT register present when the first or second signal is generated. Means are further provided for allowing the storage means to be read by the I/O channel controller when an interface control check error is detected by the I/O channel in response to I/O channel interface malfunction.

Abstract: A conditional trace system in a computer system for controlling the enablement of a trace operation in the computer system, the computer system including a set of instructions for operating said computer, the set of instructions including branch instructions, the branch instruction generating a jump signal whenever the branch instruction performs a branch operation, the conditional trace system comprising a conditional trace field in each branch instruction where the conditional trace field has either a first or second value and a first means responsive to the value of said conditional trace field and the jump signal for selectively enabling and disenabling the trace operation within the computer system.

Abstract: A timer unit that permits individual timer registers to be taken offline from the timer complex. A single register is taken offline instead of checkstopping the entire computer system due to a damaged timer, for example, thereby reducing system outages and thus providing increased availability of the system.

Abstract: A computer system having a chief system control program running in a real machine as a host where the host controls standard system control programs (SCP's) and controls virtual machines (Domains) called guests. Guests operate with interpretive execution as second-level guests. Control is transferred from a second-level guest to the guest SCP or to the chief SCP with only one control interception. Control is transferred directly between the second-level guest and the Chief SCP bypassing the first-level guest.

Abstract: Recovery of data from a store-to cache in a malfunctioning CPU, is accomplished without exercising the hardware of the malfunctioning CPU. A data path which is independent of the normal operating paths of the computer, such as a scan facility, is used to move data out of the cache into the mainstore while the malfunctioning CPU's clocks are off. A system controller controls normal transfer of data between the cache memory of the processing unit and the mainstore. A service processor is coupled to the processing unit, the mainstore, and the system controller, and is responsive to the detection of errors in the processing unit, for stopping the processing unit and moving data out of the cache memory to the mainstore through the scan facility separate from the system controller. Logic in the system controller flushes the move out queue or other storage locations in the system controller.

Abstract: A computer system having a number of circuits and error detection circuitry for detecting errors in the circuits and providing error signals. Error recovery is provided by detecting an error with checking logic, turning off system clocks and invoking error recovery software, executing recovery software to recover from the error and set an action latch, turning on system clocks, taking hardware recovery action in response to the action latch, resetting the action latch and continue processing. Action latches are used extensively throughout the computer system.

Abstract: The invention provides a method and apparatus for localizing error recovery activities to specific ones of logically parallel processes ongoing within a computer and to the initiators of error-infected ones of such processes.

Abstract: Determinism is maintained in a synchronous first system although the first system receives behaviorchanging signals from a second system running asynchronously relative to the first system. The second system refrains from sending behavior-changing signals to the first system until the first system stops its clock at a prespecified clock cycle and signals the second system of the event. The second system then downloads the behavior-changing signals into the first system and restarts the first system clock. The first system awakens to discover that the behavior-changing signals have been received during the prespecified clock cycle. This is repeated over multiple runs, and in each run the same behavior-changing signals are transferred at the same prespecified clock cycles of the first system. Deterministic behavior is thereby maintained in the first system.

Abstract: A pipeline interlock mechanism which insures the logical integrity of architected control quantities when used to access Domain Storage from Control State. A hardware Domain Interlock (DOMI) is provided to detect the start of execution in Control State of any instruction which modifies architected controls governing the access of Domain storage, and which insures that any subsequent potential access to Domain storage remains interlocked in the D-cycle until the modified controls become valid.

Abstract: In a computer system that has one or more primary processing units processing user tasks and at least one auxiliary processing unit servicing the primary processing units, feature control is performed by storing a authorization code in the auxiliary processing unit. When an operation to change the feature of the computer system is initiated, a signal, including a key code, is sent to the auxiliary processing unit. The auxiliary processing unit checks the key code against the authorization code, and enables the operation if the check is successful.

Abstract: A set of scan latches is partitioned into unique groups where each group is addressable by a group initializing circuit. The group initializing circuit initializes all the latches of an addressed group to a predefined state thereby quickly loading a test vector into the addressed group of scan latches while leaving other latches undisturbed.

Abstract: A three-dimensional microelectronic package for semiconductor chips includes alternating layers of wafer interconnect stacks and chip carrier modules. The wafer interconnect stacks provide electrical interconnections in the x, y, and z directions. The wafer interconnect stacks have conductive segments and interposers to provide signal path selection in the z-axis direction, and bump technology to provide high quality contacts between layers and continuity of the z-axis signal paths. Each layer of chip carrier modules includes a plurality of modules arranged in a preselected pattern. Each module comprises a chip carrier coupon which has a semiconductor chip mounted thereon, at least one annular spacer coupon provided on the carrier coupon and having an aperture aligned with the semiconductor chip and an opening which is aligned with a coolant discharge port in a coolant supply tube, and a lid. A coolant cavity is defined by the aperture in the spacer coupon(s).

Abstract: The times-two (.times.2) through times-nine (.times.9) multiples of a supplied multi-digit BCD number are produced using one machine cycle for performing a set-up operation and thereafter one additional machine cycle for producing all the .times.2-.times.9 multiples. A multiples generating circuit in accordance with the invention comprises: (a) an operand-storing register (OSR); (b) a multiple-storing register (MSR); (c) a multiplexer having a first input coupled to the output of the operand-storing register (OSR) and a second input coupled to the output of the multiple-storing register (MSR); (d) a .times.3 unit having an input coupled to the output of the multiplexer and an output coupled to the input of the MSR; (e) a first .times.2 unit having an input coupled to the output of the OSR; (f) a second .times.2 unit having an input coupled to the output of the first .times.2 unit; (g) a third .times.2 unit having an input coupled to the output of the second .times.2 unit; (h) a fourth .times.

Abstract: A method and apparatus for adding signed partial products without generating sign extension subfields is disclosed. The method and apparatus are particularly useful when employed in conjunction with multiplication algorithms such as the 3-bit modified Booth algorithm and the like. Rather than adding a sign extension subfield to extend the left side of each partial product row into alignment with the leftmost bit position of the sum field (e.g., the full product field), a special sign-extension "correction" factor is added to the nonextended partial products. The correction factor mimics the effect of summing the sign-extension bits which would conventionally have been added to the partial product rows. The special correction factor contains fewer bits than the total number of bits contained in all the eliminated sign extension portions, and accordingly, less computer circuitry and/or computer time is required for performing the partial product summation operation.

Abstract: A mesh comprised of intersecting control lines and clock-passing elements is distributed across the substrate of an integrated circuit (IC) chip to control the distribution of clock pulses to clock-sensitive scan latches also provided on the IC chip. The mesh consumes a relatively small portion of the surface area over the substrate. Clock-insensitive scan latches drive the control lines to create a pattern of enabled and disabled clock-passing elements such that the dynamic performance of one or more subcircuits on the IC chip can be tested through an on-chip scan testing subsystem.

Abstract: Method and apparatus are disclosed for measuring the clock offset between a reference latch point and a subject latch point in a system. In the system, an associated latch point is provided on each chip which has a subject latch point, the clock offset to which is to be measured. Test data distribution means is provided for distributing a test data signal from a test data source point to the data input of the reference latch point and to the data input of the associated latch point. Cross-transmission means are also provided for connecting together the data input of the reference latch point and the data input of the associated latch point. A pulse burst generator is connected to the clock source point in the system and a test data signal generator is connected to the test data signal source point.