Abstract: A method for fabricating a complementary metal-oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, masking the substrate to expose preselected areas for P-wells, ion implanting P-type material in the exposed areas to form P-wells so that a relatively high doping level is provided to a greater depth around composite areas within the P-wells areas and a relatively lower doping level is established under the composite layer areas with the P-wells. The ion implantation of P-type material may be accomplished in either a single stage or a two stage procedure.

Abstract: An elliptic state variable filter uses switched capacitors controlled by an arrangement of switches that provides for a frequency response independent of stray capacitors in the circuit. The filter section comprises three integrating operational amplifiers connected in series, with a feedback connection between the output of the second operational amplifier and the circuit input to the first operational amplifier. Signals via a feed forward connection from the circuit input and the outputs of the first and second operational amplifier are summed by the third operational amplifier. Transmission zeros of the filter transfer function are realized independent of poles and with a feed forward arrangement which places them inherently on the unit circle and produces infinite loss at each zero frequency despite variations in capacitor ratios in the circuit.

Abstract: An operational amplifier of MOSFET elements is disclosed which provides for a variable drive for an output stage that results in lower power dissipation and increased gain factor over comparable circuits using constant bias drive for the output stage. A bias section comprised of complementary MOS elements is connected to a single MOSFET that furnishes constant current to the signal input section of a differential amplifier section. The output of this differential amplifier is furnished by one path directly to one complementary MOSFET element of a high impedance output stage and by another path to a level shift section which provides an output to a second complementary MOSFET element of the output stage. Thus, the circuit functions under class A-B operation at low power dissipation and provides high open loop gain. Additional embodiments of the invention utilize three MOSFET elements in the level shift section or an additional output stage having an NPN transistor in combination with an N-channel MOSFET.

Abstract: A semiconductor memory device is provided comprised of an integrated array of cells formed on a substrate in conjunction with parallel spaced-apart bit lines and conductive word lines that are perpendicular to the bit lines. A plurality of V-shaped recesses are located between and extend perpendicular to adjacent parallel bit lines. Two cells share each recess and each cell includes a VMOS transistor formed by one end portion of the recess and an isolated buried source region located under the adjacent bit line. A channel stop region is located between and isolates the VMOS transistors and their respective buried source regions at opposite ends of each recess. Thus, the VMOS pass gate is shared between adjacent bit lines and bit line capacitance is minimized. Also, the VMOS pass gates are self-aligned to eliminate alignment tolerances and minimize bit line capacitance. The invention also includes an efficient method for producing a semiconductor memory device with such an array of cells.

Abstract: For an integrated circuit semiconductor device having a multiplicity of MOSFET elements, voltage-invariant capacitors, each with metal as one plate and either polysilicon or source-drain diffusion as the second plate, are created by regrowing a thin oxide layer to provide the dielectric of the capacitor during the normal MOSFET processing sequence.

Abstract: A round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final product of binary digits. The round off logic circuitry is connected in the multiplier for rounding its final product off to a predetermined binary digit without requiring the multiplier to generate any of the less significant binary digits to the right of the predetermined binary digit. Multiplier circuitry otherwise required to generate an unrounded final product prior to round off is eliminated without loss of accuracy in round off.

Abstract: A semiconductor electrically programmable read only memory device (EPROM) utilizes an array of memory cells each in the form of a single V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and word line that extends across the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and word lines by thin oxide layers. A ring of P-type conductive material around the upper end of each V-shaped recess and adjacent its surrounding N-type drain region serves to lower the required programming voltage without increasing the device threshold voltage.

Abstract: A semiconductor programmable read only memory device (PROM) utilizes an array of memory cells each having an area basically defined by the intersection of a bit line and a word address line. On a substrate of one conductivity type is an upper layer of material of the opposite conductivity within which are diffused bit lines of the same conductivity material as the substrate. The crossing address lines are conductive material formed on an insulating layer that covers the diffused bit lines and the upper layer. Each cell is a single transistor element in the form of a V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and address line that extends through the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device).

Abstract: A semiconductor memory core structure comprised of an array of cells each having a single IGFET device formed in a recess located on one side of a diffused bit line and directly above a buried storage capacitor. The diffused bit line forms one source or drain region while the buried storage capacitor forms the other source and drain region. With the channel and gate between the two source and drain regions located on only one sidewall of the recess, the gate to drain and bit line capacitance is reduced, thereby providing increased signal power and a higher signal level to a sense amplifier than heretofore available.

Abstract: A high-pass switched capacitor biquadratic filter based on the bilinear z-transform. The filter comprises first and second integrating operational amplifiers connected in series and in combination with a third operational amplifier that serves as a sample and hold and also generates one simple pole and zero pair in the circuit transfer function thereby enabling the circuit to provide for a high degree of filter efficiency in a preselected frequency range. The operational amplifiers are connected to and operate in cooperation with capacitors of a predetermined size which are switched on and off continuously by two phase clock signals supplied to the circuit. The loss characteristic of the filter can be programmed by varying the clocking frequency. Higher order filters can be obtained by the tandem connection of second order circuit sections followed by one or more first order pole-zero section.

Abstract: A switched capacitor sampled data elliptic filter for data transmission or communication systems is disclosed. The filter section comprises three integrating operational amplifiers connected in series with a negative feedback connection between the output of the second operational amplifier and the input to the first operational amplifier, which is also connected to the input voltage source. Signals via a feed forward connection from the input voltage source and the outputs of the first and second operational amplifiers are summed by the third operational amplifier. Switched capacitors in the feed forward connection, the negative feedback connection, the inputs to all three operational amplifiers and in feedback sections of the first and third operational amplifiers are all connected to a two-phase clock driver operated at a preselected frequency.

Abstract: A semiconductor read/write memory comprised of an array of cells, each having a single active element that is a IGFET device formed in a recess with one source or drain region located directly above and its other source or drain region located within a buried storage capacitor. The gate of each device is connected to an address line in the array, and transverse diffused bit lines interconnect the drains of the devices in aligned and spaced apart cells. Voltage applied via an address line activates a gate to charge its buried capacitor and store a signal when its connected bit line is also activated. Readout of stored charges is controlled by the address line through the connected bit line in the conventional manner.

Abstract: A breakdown preventing protection structure for an insulated gate field effect semiconductor device is disclosed for limiting input voltages to levels not substantially exceeding the supply voltage. A planar insulated gate field effect protection transistor is provided in series with the input. The protection transistor includes a source forming the circuit input, a drain connected to the gate of the device to be protected, and a gate electrode connected to the supply voltage which also supplies the device to be protected. A shunting protective diode may be included at the source of the protection transistor to limit negative input voltages to the diode threshold voltage and positive input voltages to the reverse avalanche breakdown of the protective diode. The protection circuit is particularly well suited to protect V-groove metal oxide semiconductor devices which have breakdown voltages well below breakdown voltages of conventional planar MOS transistor devices.

Abstract: A method for combining a semiconductor device with a printed circuit board or substrate which eliminates the need for conventional semiconductor packaging and connectors for same on the board and thereby makes possible a relatively small and thin assembly adaptable for space limited electronic products. The semiconductor device is fixed to a carrier which is installed and secured within a hold in the circuit board. Terminal pads of the device are wire bonded to terminals on the substrate, and the connecting wires and die are completely encapsulated within a plastic material.

Abstract: In a metal oxide silicon memory device having an array of static memory cells, a sense amplifier for detecting signals produced by the cells connected between complementary bit lines. The amplifier includes a translator section that shifts the normally high bit and bit voltage levels to a lower voltage level at the control gates of signal output devices connected to output bus lines. Each output bus line has only a single device impedance to ground rather than the normally required stacked or series arrangement of control elements. This provides a low impedance to ground for one of the output bus lines whle the signal variation around threshold provides a relatively high impedance to ground on the other bus line, thereby providing fast response times.

Abstract: A visual tuning-aid system for aligning an electronic timepiece to a correct reference frequency is disclosed. A reference oscillator in the system provides a reference signal at a precisely fixed predetermined frequency which is, or is converted to, the correct alignment frequency for the timepiece. A sensor electrostatically detects a time base signal in the timepiece and a bandpass amplifier removes any extraneous signals. The reference signal and the time base signal are provided to a phase shift indicating device of a multiphase motor in the system which provides a visual display, the movement of which is proportional to the rate of phase change between the reference signal and the time base signal. Alignment of the timepiece to the correct frequency stops the phase change and thereupon the visual display stops moving.

Abstract: An initializing circuit for automatically providing a pulse of a duration sufficient to initialize all the relevant storage elements in an electronic calculator computing system having one or two power supplies. It comprises a power-on pulse generator controlled by two phase clock buffers utilizing a feed-back loop including a bit of delay to guarantee a minimum of one bit time duration for the power-on level. The two phase clock buffers are activated at turn-on to remain in a steady state by a power-on level detecting sub-circuit to control the pulse generator. When a one bit pulse is insufficient to initialize the system, a flip-flop and a counter may be used to generate a longer pulse.

Abstract: An assembly of electronic components and a method of packaging such components to form a solid state time-keeping device capable of being housed in watch cases having different external configurations. The assembly includes a sub-assembly component which combines and interconnects an integrated semiconductor device with other discrete elements required to perform basic timing function in a compact package. This sub-assembly and the various other electronic components are readily removable and interchangeably replaceable with simple jeweler's hand tools.

Abstract: A multi-position switch particularly adaptable for an electronic watch comprises a movable plate or disk mounted within a cup-like body and rotatable about an axis to different positions for accomplishing various setting or operating modes. Fixed contacts on the inside of the switch plate are spaced apart but electrically connected so that when the plate is rotated to certain positions relative to its central axis the contacts are aligned for engagement with a particular pair of a series of terminals located on the inside planar surface of the switch body and connected through the body to the internal circuitry of the device. The interconnection of certain pairs of terminals accomplished by the contacts activates internal circuitry of the device to produce the desired operating function or mode.