Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: In one example, a semiconductor device comprises a main substrate comprising a first side and a main conductive structure, and a first component module over the first side of the main substrate. The first component module comprises a first electronic component and a first module encapsulant contacting a lateral side of the first electronic component. The semiconductor device further comprises a second component module over the first side of the main substrate. The second component module comprises a second electronic component and a second module encapsulant contacting a lateral side of the second electronic component. The semiconductor device further comprises a main encapsulant over a first side of the main substrate and between the first component module and the second component module. Other examples and related methods are also disclosed herein.

Abstract: An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.

Abstract: A packaged electronic device includes a substrate comprising a die pad and a lead spaced apart from the die. An electronic device is attached to the die pad top side. A conductive clip is connected to the substrate and the electronic device, and the conductive clip comprises a plate portion attached to the device top side with a conductive material, a clip connecting portion connected to the plate portion and the lead, and channels disposed to extend inward from a lower side of the plate portion above the device top side. The conductive material is disposed within the channels. In another example, the plate portion comprises a lower side having a first sloped profile in a first cross-sectional view such that an outer section of the first sloped profile towards a first edge portion of the plate portion is spaced away from the electronic device further than an inner section of the first sloped profile towards a central portion of the plate portion. Other examples and related methods are also disclosed herein.

Abstract: In one example, a semiconductor device, comprises a first redistribution layer (RDL) substrate comprising a first dielectric structure and a first conductive structure through the first dielectric structure and comprising one or more first conductive redistribution layers, an electronic component over the first RDL substrate, wherein the electronic component is coupled with the first conductive structure, a body over a top side of the first RDL substrate, wherein the electronic component is in the body, a second RDL substrate comprising a second dielectric structure over the body, and a second conductive structure through the second dielectric structure and comprising one or more second conductive redistribution layers, and an internal interconnect coupled between the first conductive structure and the second conductive structure. Other examples and related methods are also disclosed herein.

Abstract: In one example, a semiconductor device structure relates to an electronic device, which includes a device top surface, a device bottom surface opposite to the device top surface, device side surfaces extending between the device top surface and the device bottom surface, and pads disposed over the device top surface. Interconnects are connected to the pads, and the interconnects first regions that each extend from a respective pad in in an upward direction, and second regions each connected to a respective first region, wherein each second region extends from the respective first region in a lateral direction. The interconnects comprise a redistribution pattern on the pads. Other examples and related methods are also disclosed herein.

Abstract: In one example, an electronic device comprises a base substrate comprising a base substrate conductive structure, a first electronic component over a first side of the base substrate, an encapsulant over the first side of the base substrate, wherein the encapsulant contacts a lateral side of the electronic component, an interposer substrate over a first side of the encapsulant and comprising an interposer substrate conductive structure, and a vertical interconnect in the encapsulant and coupled with the base substrate conductive structure and the interposer substrate conductive structure. A first one of the base substrate or the interposer substrate comprises a redistribution layer (RDL) substrate, and a second one of the base substrate or the interposer substrate comprises a laminate substrate. Other examples and related methods are also disclosed herein.

Abstract: A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A<B and 0=<C<1/2×D. The shape of the via aperture prevents solder deformation of the solder column formed from the solder ball as well as prevents solder bridging between adjacent solder columns.

Abstract: In one example, a semiconductor device can comprise a unit substrate comprising a unit conductive structure and a unit dielectric structure, and an electronic component coupled to the unit conductive structure. The unit substrate can comprise a portion of a singulated subpanel substrate of a panel substrate. Other examples and related methods are also disclosed herein.

Abstract: In one example, a semiconductor device includes a substrate having leads that include lead terminals, lead steps, and lead offsets extending between the lead steps so that at least some lead steps reside on different planes. A first electronic component is coupled to a first lead step side and includes a first electronic component first side, and a first electronic component second side opposite to the first electronic component first side. A second electronic component is coupled to a second lead step side, and includes a second electronic component first side, and a second electronic component second side opposite to the second electronic component first side. An encapsulant encapsulates the first electronic component, the second electronic component, and portions of the substrate. The lead terminals are exposed from a first side of the encapsulant. Other examples and related methods are also disclosed herein.

Abstract: In one example, a semiconductor device includes a substrate having a substrate first side, a substrate second side opposite to the substrate first side, and a conductive structure including internal terminals over the substrate first side; and external terminals over the substrate second side and coupled to the internal terminals. An electronic component includes an electronic component first side, an electronic component second side opposite to the electronic component first side, and an electronic component lateral side connecting the electronic component first side to the electronic component second side. The electronic component second side is coupled to one or more of the internal terminals. A guide structure is over the substrate first side and can include an inner portion that is laterally inward from the electronic component lateral side and an outer portion that is laterally outward from the electronic component lateral side.

Abstract: A method for forming a packaged electronic device includes providing a substrate having a first major surface and an opposing second major surface. The method includes attaching an electronic device to the first major surface of the substrate and providing a first conductive structure coupled to at least a first portion of the substrate. The method includes forming a dielectric layer overlying at least part of the first conductive structure. The method includes forming a conductive layer overlying the dielectric layer and connected to a second portion of the substrate. The first conductive structure, the dielectric layer, and conductive layer are configured as a capacitor structure and further configured as one or more of an enclosure structure or a stiffener structure for the packaged electronic device.

Abstract: In one example, an electronic device includes a substrate, which has a dielectric structure includes a dielectric structure top side and a dielectric structure bottom side opposite to the dielectric structure top side, and a conductive structure comprising a protruded via that extends from the dielectric structure bottom side. An electronic component is coupled to the conductive structure at the dielectric structure top side, and a terminal is coupled to the protruded via such that the protruded via extends into the terminal. Other examples and related methods are also disclosed herein.

Abstract: In one example, a semiconductor device comprises a first base substrate comprising a first base conductive structure, a first encapsulant contacting a lateral side of the first base substrate, a redistribution structure (RDS) substrate over the base substrate and comprising an RDS conductive structure coupled with the first base conductive structure, a first electronic component over the RDS substrate and over a first component terminal coupled with the RDS conductive structure, and a second encapsulant over the RDS substrate and contacting a lateral side of the first electronic component. Other examples and related methods are also disclosed herein.

Abstract: A method for forming packaged electronic device structure includes providing a conductive leadframe. The leadframe can include a die pad with a first major surface and a second major surface opposite to the first major surface, and a plurality of conductive leads. The method can include coupling an electronic device to the plurality of conductive leads. The method can include providing an antenna structure, which can include a conductive pillar structure and an elongated conductive beam structure. The method can include providing a package body encapsulating the electronic device, at least portions of each conductive lead, and at least portions of the die pad.

Abstract: A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.

Abstract: In one example, a packaged electronic device includes a molded substrate. The molded substrate includes a conductive structure having an edge lead with an edge lead outward side and an edge lead inward side opposite to the edge lead outward side, and an inner lead having an inner lead outward side and an inner lead inward side opposite to the inner lead outward side. The molded substrate includes a substrate encapsulant covering a lower portion of the edge lead inward side, a lower portion of the inner lead inward side, and a lower portion of the inner lead outward side. An upper portion of the edge lead outward side and an upper portion of the inner lead outward side are exposed from the substrate encapsulant. An electronic component is connected to the edge lead and the inner lead. A body encapsulant covers the electronic component and portions of the conductive structure.

Abstract: In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Abstract: Methods and system for flip chip alignment for substrate and leadframe applications are disclosed and may include placing a semiconductor die on bond fingers of a metal leadframe, wherein at least two of the bond fingers comprise one or more recessed self-alignment features. A reflow process may be performed on the semiconductor die and leadframe, thereby melting solder bumps on the semiconductor die such that a solder bump may be pulled into each of the recessed self-alignment features and aligning the solder bumps on the semiconductor die to the bond fingers. The recessed self-alignment features may be formed utilizing a chemical etch process or a stamping process. A surface of the recessed self-alignment features or the bond fingers of the metal leadframe may be roughened. A solder paste may be formed in the recessed self-alignment features prior to placing the semiconductor die on the bond fingers of the metal leadframe.

Abstract: In one example, a semiconductor device, comprises a first redistribution layer (RDL) substrate comprising a first dielectric structure and a first conductive structure through the first dielectric structure and comprising one or more first conductive redistribution layers, an electronic component over the first RDL substrate, wherein the electronic component is coupled with the first conductive structure, a body over a top side of the first RDL substrate, wherein the electronic component is in the body, a second RDL substrate comprising a second dielectric structure over the body, and a second conductive structure through the second dielectric structure and comprising one or more second conductive redistribution layers, and an internal interconnect coupled between the first conductive structure and the second conductive structure. Other examples and related methods are also disclosed herein.