Abstract: An optical sensor arrangement has an integrator, a photodiode for providing a current corresponding to a first polarity, a comparator coupled to the integrator for comparing a voltage with a threshold voltage to provide a comparison output, a reference charge circuit and a control unit. The reference charge circuit is coupled to the integrator for selectively providing first charge packages of a first size or second charge packages of a second size. The control unit is configured to control operation in a calibration phase, in an integration phase and in a residual measurement phase. During the calibration phase, the reference charge circuit provides one of the first charge packages and one or more of the second charge packages to the integrator until the comparison output changes. A reference number is determined corresponding to a number of the second charge packages provided.

Abstract: An optical proximity sensor arrangement comprises a first sensor unit with a first emitter and a first detector and a second sensor unit with a second emitter and/or a second detector. The first detector is configured to detect light being emitted by the first emitter and, if applicable, by the second emitter, and being at least partially reflected. If applicable, the second detector is configured to detect light being emitted by the first emitter and being at least partially reflected. A distance between the first emitter and the first detector is, if applicable, less than a distance between the first detector and the second emitter and, if applicable, less than a distance between the first emitter and the second detector.

Abstract: A semiconductor device has a semiconductor substrate and a first metallization stack arranged on the substrate. The substrate has and/or carries a plurality of electronic circuit elements. The first metallization stack has electrically insulating layers and at least one metallization layer. The semiconductor device further has a second metallization stack arranged on the first metallization stack and comprising further electrically insulating layers and an optical waveguide layer. The optical waveguide layer has at least one optical waveguide structure. Furthermore, one of the electrically insulating layers and one of the further electrically insulating layers are in direct contact with each other and form a pair of directly bonded layers.

Abstract: An optical driver arrangement (10) comprises a comparator (11) and a pulse generator (15). The comparator (11) comprises a first input (12) for receiving a sensed output signal (S1) derived from a sensor signal (S2) generated by a light sensor (24), a second input (13) for receiving a reference signal (S3) and a comparator output (14) for providing a comparator signal (S4). The pulse generator (15) comprises a control input (16) coupled to the comparator output (14) and a generator output (22) for providing a driver signal (S5) to a light source (21). The driver signal (S4) comprises a series of at least one pulse and a parameter of the driver signal (S4) is controlled by the comparator signal (S4).

Abstract: A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.

Abstract: A communication device (10) comprises a conductor (11), a transceiver (12) coupled to the conductor (11) and a data processing unit (13) that is coupled to the transceiver (12). The communication device (10) is configured to determine a strength signal (ST) depending on a receiver signal (SR) received via the conductor (11) and to determine a proximity signal (SP) depending on a proximity of a body to the communication device (10). The data processing unit (13) is configured to generate a disable signal (STO) depending on at least a value of the strength signal (ST) and on at least a value of the proximity signal (SP).

Abstract: A top surface of a substrate is provided with a detection element for detecting electromagnetic radiation. A refractive element is formed by a portion of a cover element, which is attached to the substrate, so that the refractive element is arranged facing the detection element. The refractive element may be arranged within a recess of the cover element, so that a cavity is formed between the detection element and the refraction element.

Abstract: A method for passive optical motion detection uses an optical sensor arrangement comprising an optical sensor having at least one signal channel. The optical sensor arrangement is initialized for repeated signal acquisition and an initial frame comprising a tuple of sensor data is collected from the at least one signal channel. The initial frame is set as a previous frame. A loop of motion detection is entered and the following steps are repeated. First, a current frame comprising another tuple of sensor data is collected from the at least one signal channel. Then, a motion parameter is computed from a motion metric depending on the current and previous frames. The so computed motion parameter is compared with a threshold value. A motion event parameter is set depending on the comparison of the motion parameter with the threshold value. The current frame is set as previous frame so that the loop can start all over again.

Abstract: An optical proximity sensor arrangement comprises a semiconductor substrate (100) with a main surface (101). A first integrated circuit (200) comprises at least one light sensitive component (201). The first integrated circuit is arranged on the substrate at or near the main surface. A second integrated circuit (300) comprises at least one light emitting component (301), and is arranged on the substrate at or near the main surface. A light barrier (400) is arranged between the first and second integrated circuits. The light barrier being designed to block light to be emitted by the at least one light emitting component from directly reaching the at least one light sensitive component. A multilayer mask (500) is arranged on or near the first integrated circuit and comprising a stack (501) of a first layer (502) of first elongated light blocking slats (503) and at least one second layer (504) of second elongated light blocking slats (505).

Abstract: An amplifier arrangement has a first differential stage with a first transistor pair, a second differential stage with a first and a second transistor pair, each pair having a common source connection. The amplifier arrangement further has a first complementary differential stage with a transistor pair having opposite conductivity type, and a second complementary differential stage with a first and a second transistor pair of the complementary conductivity type. The first and the second complementary differential stage are connected symmetrically compared to the first and the second differential stage. The transistors of the second differential stage and the second complementary differential stage are symmetrically connected to form respective first, second, third and fourth current paths. A pair of output terminals is coupled to the first and the fourth current path. Gate terminals of the transistors are coupled to a respective pair of input terminals.

Abstract: An amplifier circuit (AC) for amplifying an output signal (OS) of a capacitive sensor (M) comprises a first input terminal (AIN) to receive the output signal (OS) of the capacitive sensor (M) and a second input terminal (BIN) to receive a bias voltage (Vbias) of the capacitive sensor (M). The amplifier circuit (AC) comprises an amplifier (A) for amplifying the output signal (OS) and a control circuit (CF) arranged in a feedback loop (FL) of the amplifier (A) being configured to control a DC voltage level at an input connection (A1) of the amplifier (A). A bias voltage sensing circuit (BVS) senses a change of the level of the bias voltage (Vbias) at the second input terminal (BIN) and changes the bandwidth of the feedback loop (FL) in dependence on the sensed change of the level of the bias voltage (Vbias).

Abstract: The invention relates to a method for determining at least one blood pressure value of a subject. According to the invention, a heartbeat signal of a subject, in particular an ECG, is determined by means of a heartbeat measuring arrangement and transmitted to a circulation parameter determination unit, wherein the circulation parameter determination unit determines at least one value of an autonomic tone, in particular a vagal tone and/or a heart rate variability and/or a sympathetic tone and/or an autonomic quotient, from a determined time profile of the heartbeat signal, wherein the circulation parameter determination unit determines the at least one blood pressure value taking into account the at least one value of the autonomic tone, and the determined blood pressure value is output.

Abstract: The method comprises providing a time-to-digital converter with a measurement period (3) for registration of events (1), and selecting time intervals of independent durations (4), each of the durations being independent of the registration of events. At each registration of an event, the time-to-digital converter is blocked from further registration for one of the time intervals of independent duration. Thus the recorded lengths of the time intervals (11, 13, 14, 16) corresponding to the occurrence of the events within each measurement period are uniformly distributed and a time-domain bias is avoided. The time-to-digital converter circuit includes a controlled gate for blocking the time-to-digital converter.

Abstract: A circuit arrangement for an optical monitoring system comprises a driver circuit configured to generate at least one driving signal for driving a light source and a detector terminal for receiving a detector current. The circuit arrangement further comprises a current source configured and arranged to generate at the detector terminal a reduction current. The reduction current has an amplitude which is given by a base value whenever none of the least one driving signal assumes a value suitable for activating the light source and by a sum of the base value and a reduction value otherwise. The circuit arrangement also comprises a processing unit configured to generate an output signal depending on a combination of the detector current and the reduction current.

Abstract: A controller (1) to reduce integral non-linearity errors of a magnetic rotary encoder (2) comprises a position error determining unit (20) to determine a plurality of time marks (P0, . . . , Pk) specifying a respective time at which a moving device (3) reaches a respective one of predefined positions (?0, . . . , ?k). The position error determining unit (20) calculates a plurality of error correction parameters (B[0], . . . , B[k]) in dependence on the time marks (P0, . . . , Pk). An error compensation unit (10) of the controller determines a respective error compensated position parameter (?start_comp, ?0_comp, . . . , ?n_comp) for each position parameter (?start, ?0, . . . , ?n) received from the encoder (2) in dependence on the respective position parameter (?start, ?0, . . . , ?n) and the respective error correction parameter (B[0], . . . , B[k]).

Abstract: An avalanche diode arrangement (10) comprises an avalanche diode (11) that is coupled to a first voltage terminal (16) and to a first node (13), an event detector (14) for detecting a trigger event of the avalanche diode (11) and being coupled to the first node (13), a quenching circuit (15) that is coupled to the first node (13), and a detection circuit (20) coupled to the first node (13). The detection circuit (20) is configured to provide a detection signal (SVC2) that depends on a value of a node voltage (SVA) at the first node (13).

Abstract: A signal processing arrangement has a signal input for connecting a capacitive sensor. An amplifier circuit is coupled between the signal input and a feedback point. A loop filter is coupled downstream to the feedback point. A quantizer is connected downstream to the loop filter and provides a multi-bit output word. The multi-bit output word consists of one or more higher significance bits and one or more lower significance bits. A first feedback path is coupled between a quantizer and the feedback point for providing a first feedback signal to the feedback point being representative of the one or more lower significance bits. A second feedback path is coupled to the quantizer for providing a second feedback signal to the signal input being representative of the one or more higher significance bits.

Abstract: A semiconductor body of a first type of conductivity is formed including a base layer, a first further layer on the base layer and a second further layer on the first further layer. The base layer and the second further layer have an intrinsic doping or a doping concentration that is lower than the doping concentration of the first further layer. A doped region of an opposite second type of conductivity is arranged in the semiconductor body, penetrates the first further layer and extends into the base layer and into the second further layer. Anode and cathode terminals are electrically connected to the first further layer and the doped region, respectively. The doped region can be produced by filling a trench with doped polysilicon.

Abstract: A well of a first type of conductivity is formed in a semiconductor substrate, and wells of a second type of conductivity are formed in the well of the first type of conductivity at a distance from one another. By an implantation of dopants, a doped region of the second type of conductivity is formed in the well of the first type of conductivity between the wells of the second type of conductivity and at a distance from the wells of the second type of conductivity. Source/drain contacts are applied to the wells of the second type of conductivity, and a gate dielectric and a gate electrode are arranged above regions of the well of the first type of conductivity that are located between the wells of the second type of conductivity and the doped region of the second type of conductivity.

Abstract: A digital-to-analog converter comprises a converter output (11), a dummy output (12), a first number N of current sources (13-17), a first switching arrangement (18), a first current divider (24), a second switching arrangement (31) and a second current divider (60). The current sources (13-17) are coupled via the first switching arrangement (18) to the converter output (11), the dummy output (12) or to an input current terminal (25) of the first current divider (24). The output current terminals (26-30) of the first current divider (24) are coupled via the second switching arrangement (31) to the converter output (11), the dummy output (12) or to an input current terminal (61) of the second current divider (60). The output current terminals (63-66) of the second current divider (60) are coupled to the converter output (11) or the dummy output (12).