Abstract: A laterally coupled isolator includes a pair of isolator traces provided in a common dielectric layer and separated by a distance that defines the isolation strength of the system. Circuit designers can vary the lateral distance to tailor isolation rating to suit individual design needs. A second embodiment includes a semiconductor substrate, provided below the isolator traces that includes a communication circuit electrically coupled to one of the isolator devices.

Abstract: A current amplifier is disclosed. The circuit has differential input and output and can be implemented in CMOS or bipolar integrated-circuit technologies. The input current is injected into a pair of primary branches, and is re-used at the output of the circuit without changing its natural flow, thus contributing to the overall current gain. A pair of secondary branches is connected to the primary branches in such a way as to provide currents proportional to the input currents according to a scaling factor dictated by the geometry of the transistors. The outputs of the secondary branches are cross-coupled relative to the outputs of the primary branches, in this way ensuring maximum current gain by the summing of the primary and secondary signal currents at the circuit output, without consuming additional DC power.

Abstract: A switching power converter circuit comprises an input port, a first circuit supply rail having a first positive voltage greater than circuit ground, a second circuit supply rail having a second positive voltage greater than circuit ground, and an inductor electrically coupled to the input port, wherein inductor current flows in a first direction through the inductor to generate the first circuit supply rail and flows in an opposite direction through the inductor to generate the second circuit supply rail.

Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Abstract: When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an addition source of error which can significantly affect the performance of the SAR ADC. Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word for each bit under test to correct for the error. Such a calibration technique can lessen the need to store a calibration word for each possible output word to correct the additional source of error. Furthermore, another calibration technique can expose the effective bit weight of each bit under test without having to generate the plurality of special input voltages.

Abstract: A successive approximation register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal independent (can be easily measured and corrected/calibrated).

Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Abstract: A hybrid, translinear amplifier has at least one gain stage including first and second gain transistors, at least a first load transistor electrically coupled to the first gain transistor and at least a second load transistor electrically coupled to the second gain transistor, and load resistors electrically coupled to the load transistors. A hybrid, translinear amplifier with selectable gain has a first hybrid, translinear amplifier cell having at least first and second load transistors, each load transistor having a load resistor, at least one additional hybrid, translinear amplifier cell having at least third, fourth, fifth and sixth load transistors, each load transistor having a load resistor, at least two switches electrically coupled to the amplifier cells to allow selection of one of the amplifier cells, and a differential output signal having a gain corresponding to a selected amplifier cell.

Abstract: A motor driver may include a controller, a space vector modulator, a converter and a detector. The space vector modulator may generate driving signals under control of the controller according to a space vector pulse width modulation (“SVPWM”) scheme. The converter may derive AC signals from the driving signals received from the space vector modulator and may output the AC signals to the USM motor. The detector may generate feedback signals representing current and voltage supplied to the USM motor. The controller may revise estimates of space vectors, based on measurements from the detector, to control the space vector modulator to adjust frequencies, amplitudes, or phase angles of the plurality of AC signals.

Abstract: Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.

Abstract: A drive system for multiple LED strings powered by a common line voltage. Current control circuits are connected in series with respective LED strings; each current control circuit includes a drive transistor (typically a FET) which causes a desired LED string current to be conducted. In one embodiment, the current conducted by a selected one of the LED strings is controlled by the line voltage regulation loop, while the currents conducted by the remaining LED strings are controlled by respective local current loops, thus avoiding conflicts between the local current and line voltage regulation loops. The LED string to be current regulated by the line voltage regulation loop can be determined by a variety of criteria, such as the current control circuit having the maximum FET gate voltage, the minimum FET source voltage, the minimum FET drain voltage, the maximum FET gate-source voltage, or the minimum FET drain-source voltage.

Abstract: Apparatus and methods for switch-coupled oscillators are disclosed. In certain implementations, an oscillator system includes a primary oscillator, one or more auxiliary oscillators, one or more switching circuits, and an oscillator control circuit. The oscillator control circuit can be used to control the one or more switching circuits to selectively couple the primary oscillator to all or a portion of the one or more auxiliary oscillators. The oscillator control circuit can also disable any auxiliary oscillators that are decoupled from the primary oscillator to reduce power consumption. By selecting a number of auxiliary oscillators to couple to the primary oscillator, the oscillator system can have a configurable phase noise versus power consumption profile.

Abstract: Apparatus and methods for chopper amplifiers are provided herein. In certain configurations, a chopper amplifier includes at least one differential transistor bank including a selection circuit and a plurality of transistors. The selection circuit can select a first portion of the transistors for operation in a first transistor group and a second portion of the transistors for operation in a second transistor group. During calibration, the chopper amplifier's input offset can be observed for different transistor configurations of the differential transistor banks. Although the transistors of a particular bank can be designed to have about the same drive-strength and/or geometry, the chopper amplifier can have a different input offset in different transistor configurations due to manufacturing mismatch between transistors, such as process variation.

Abstract: Practical electronics such as amplifiers or voltage references can have circuit imbalances due to manufacturing imperfections. For example, amplifiers can have an undesirable offset voltage. The offset voltage might also drift with temperature making the design of these devices difficult. Disclosed are techniques which decrease the amount of offset voltage which provide predictability of device parameters over a range of temperatures.

Abstract: In an example, there is disclosed a system and method for detecting and correcting error in a quadrature receiver (QR). The QR may include a receiver channel operable to divide a received RF signal into I and Q channels. The receiver channel may include error sources, such as (in sequence) pre-demodulation (PD) error, LO mixer error, and baseband (BB) error. Test tones may be driven on the receiver channel at a plurality of test frequencies, and a quadrature error corrector may be provided to detect error from each source. Upon receiving an RF signal, the quadrature error corrector may apply correction coefficients to correct each source of error in reverse sequence (BB, LO, PD).

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Abstract: In an example, there is disclosed a system and method for detecting and correcting error in a quadrature receiver (QR). The QR may include a receiver channel operable to divide a received RF signal into I and Q channels. The receiver channel may include error sources, such as (in sequence) pre-demodulation (PD) error, LO mixer error, and baseband (BB) error. Test tones may be driven on the receiver channel at a plurality of test frequencies, and a quadrature error corrector may be provided to detect error from each source. Upon receiving an RF signal, the quadrature error corrector may apply correction coefficients to correct each source of error in reverse sequence (BB, LO, PD).

Abstract: A method for aligning an opto-electronic component in an IC die with an optical port is disclosed. This is achieved, in various embodiments, by forming alignment features in the IC die that can mate with complementary alignment features of the optical port. The formation of alignment features can be performed at the wafer level during fabrication of the IC die. An optical signal carrier may be optically coupled to the optical port such that the signal carrier may communicate optically with the opto-electronic component.

Abstract: A tunable impedance circuit can include a fixed impedance and one or more impedance selection circuits. Each impedance selection circuit can include a first impedance connected to a first interface terminal, a second impedance connected to a second interface terminal, and a plurality of series-connected transistors connected between the first and second impedances. Each impedance selection circuit can also include a plurality of drive impedance networks connected to gates, sources, drains, bodies, and isolation regions of the series-connected transistors, and a control circuit to provide a plurality of control signals to the drive impedance networks to turn on and turn off the series-connected transistors. For each impedance selection circuit, turning on and turning off the respective plurality of series-connected transistors can bring the series combination of the respective first and second impedances into and out of electrical communication with, e.g., into and out of parallel with, the fixed impedance.