Abstract: A data channel includes a power constrained first channel portion to receive energy from a limited power source and a non-power constrained second channel portion to receive energy from a different power source than the first channel portion. The first channel portion includes an ADC circuit to output an ADC data sample, a first transmitter circuit configured to serially transmit data that includes ON bits and OFF bits, and logic circuitry configured to derive transmit data from the ADC data sample. The transmitter circuit uses more energy transmitting the ON bits than the OFF bits, and the derived transmit data has a reduced number of the ON bits from the ADC data sample. The second channel portion includes a first receiver circuit to receive the derived transmit data from the first transmitter circuit of the first channel portion.

Abstract: Techniques, methods, circuits, and systems are provided for providing stabilization for a circuit. One example system includes a switching converter coupled to a power source; a low-pass filter coupled to a load device; a direct current (DC) path; and an alternating current (AC) path, where the DC path and the AC path are provided between the switching converter and the low-pass filter, and where the AC path provides a non-phased information signal to be used to compensate for a phase delay occurring in the DC path. In a more specific implementation, the DC path can be configured to provide control, at low frequency, for an output to the load device. In addition, an error amplifier can be to the DC path and the AC path, where the low-pass filter and the error amplifier can be configured to determine a switchover between the AC path and DC path.

Abstract: A multi-phase regulator circuit includes one or more switching converter circuits. Each switching converter circuit includes a transformer including a primary winding and a multi-segment secondary winding, a primary side switch circuit configured to connect the primary winding to an input of the multi-phase regulator circuit, and multiple secondary side circuits including multiple coupled-inductor circuits. Each coupled-inductor circuit includes a first winding magnetically coupled to a second winding. Each segment of the transformer multi-segment secondary winding is operatively coupled to the first winding of a coupled-inductor circuit and each of the first windings is connected to an output of the multi-phase regulator circuit.

Abstract: The present disclosure relates to configuring at least one pair of devices in a physical unclonable function (PUF) apparatus and reading out at least one pair of devices for determining a persistent random PUF output. The pair of devices may be readout by measuring a physical difference between the devices/components caused by random manufacturing differences, which may then be used to determine a persistence random PUF output. Configuring the pair of devices includes measuring the random manufacturing difference and, based on that measurement, setting a readout condition for the pair of devices, which dictates aspects of the readout process that should be used for that pair of devices. Each time the pair of devices is readout in the future, it may be readout in accordance with the condition that was set at configuration.

Abstract: Systems and methods are provided for synchronizing a lower-power idle state. The systems and methods perform operations comprising: initializing, by a master physical layer (PHY) controller, a connection over a network with a slave PHY controller; during initialization, synchronizing a low power idle (LPI) timer of the master PHY controller with a LPI timer of the slave PHY controller; establishing an offset between the LPI timer of the master PHY controller and the LPI timer of the slave PHY controller; and after synchronizing the timer of the master PHY controller with the LPI timer of the slave PHY controller, establishing a link between the master PHY controller and the slave PHY controller to enable the master PHY controller and the slave PHY controller to exchange data.

Abstract: A package is disclosed. The package includes a carrier that comprises a first conductive layer on a first side and a second conductive layer on a second side opposite the first side. The first conductive layer comprises wire bonding pads. The package also includes a semiconductor die that is flip chip mounted on the first side of the carrier.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: An integrated circuit comprising a plurality MAC pipelines wherein each MAC pipeline includes: (i) a plurality of MACs connected in series and (ii) a plurality of data paths including an accumulation data path, wherein each MAC includes a multiplier to multiply to generate product data and an accumulator to generate sum data. The integrated circuit further comprises a plurality of control/configure circuits, wherein each control/configure circuit connects directly to and is associated with a MAC pipeline, wherein each control/configure circuit includes an accumulation data path which is configurable to directly connect to the accumulation data path of the MAC pipeline to form an accumulation ring when the control/configure circuit is configured in an accumulation mode, and an output data path configurable to directly connect to the output of the accumulation data path of the MAC pipeline when the control/configure circuit is configured in an output data mode.

Abstract: A voltage monitor circuit that signals if an input voltage is above or below an internally established reference level proportional to the bandgap voltage of silicon. The voltage monitor circuit mitigates main error sources generally associated with bandgap reference generation such that high accuracy and good performance may be achieved at low power cost. The techniques allow voltage monitors (e.g., brown-out and power on reset (POR) detectors) to be implemented with higher accuracy, lower power consumption, smaller area cost, and support to lower supply voltage than other solutions.

Abstract: An integrated circuit including a multiplier-accumulator circuit pipeline including a plurality of MAC circuits. Each MAC circuit includes: (A) a multiplier circuit to multiply first input data and filter weight data to generate and output first product data having a floating point data format, and (B) a coarse floating point accumulator circuit including: (1) an alignment shift circuit to shift at least one field of the first product data and generate shifted first product data, and (2) fixed point addition circuitry, coupled to the alignment shift circuit, to add second input data and the shifted first product data using the fixed point addition circuitry. The plurality of MAC circuits of the multiplier-accumulator circuit execution pipeline, in operation, each perform a plurality of multiply operations and accumulate operations to process the first input data and generate processed data therefrom.

Abstract: Several current sensing techniques are described that may be used to obtain an accurate current signal, which may help to achieve the best performance with a trans-inductor voltage regulator (TLVR) topology. The techniques may have the coupling effect from the secondary side included, so the current sensing signal is accurate for the regulation and other functions related to the current signal. The current sensing techniques may have more accurate gain and phase information in the middle frequency and high frequency ranges. The coupling effect from the secondary side may be well represented in the current sensing signal. The advantages of TLVR topology may be enhanced with accurate current information.

Abstract: Compact packages including microelectromechanical system (MEMS) devices and multiple application specific integrated circuits (ASICs) are described. These packages are sufficiently small to be applicable to contexts in which space requirements are particularly strict, such as in consumer electronics. These packages involve vertical die stacks. A first ASIC may be positioned on one side of the die stack and another ASIC may be positioned on the other side of the die stack. A die including a MEMS device (e.g., an accelerometer, gyroscope, switch, resonator, optical device) is positioned between the ASICs. Optionally, an interposer serving as cap substrate for the MEMS device is also positioned between the ASICs. In one example, a package of the types described herein has an extension of 2 mm×2 mm in the planar axes and less than 500-800 ?m in height.

Abstract: Apparatus and methods for logarithmic current to voltage conversion are disclosed herein. In certain embodiments, a logarithmic current to voltage converter includes an input terminal that receives an input current, an output terminal that provides a logarithmic output voltage, a first field-effect transistor (FET) having a gate connected to the input terminal, a first bipolar transistor having a collector connected to the input terminal and an emitter connected to the output terminal, and a stacked transistor connected to the output terminal and to the first FET to form a feedback loop. For example, the stacked transistor can correspond to a second bipolar transistor having a collector connected to the output terminal and a base connected to the source of the first FET, or to a second FET having a drain connected to the output terminal and a gate connected to the source of the first FET.

Abstract: There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.

Abstract: A system for reducing clock jitter may include first jitter reducing circuitry. The first jitter reducing circuitry may be arranged between an input clock signal node carrying an input clock signal and an output clock signal node carrying an output clock signal. The first jitter reducing circuitry may include a first intermediate input clock signal node and a first intermediate output clock signal node. The first jitter reducing circuitry may include a first clock delay circuit, which may be configured to: (1) delay a first intermediate input clock signal received on the first intermediate input clock signal node by an odd integer multiple of one half of a period, and (2) invert the first intermediate input clock signal. The first jitter reducing circuitry may also include a first connection, which may be from the first intermediate output clock signal node to the first intermediate input clock signal node.

Abstract: Various examples are directed to a System on a Chip (SOC) and methods of operating the same. The SOC may access firmware code from a boot Read-Only Memory (ROM) of the SOC. The firmware code may comprise a plurality of functional blocks. The SOC may determine that firmware patching is active for the SOC and access patch data from a non-volatile memory of the SOC. The SOC may determine that a first functional block of the firmware code has been patched and access first patch code from the patch data. The first patch code may be associated with the first functional block. The SOC may execute the first patch code.

Abstract: Apparatus and methods for nanoplasma switches are disclosed. In certain embodiments, a nanoplasma switching system includes a nanoplasma radio frequency (RF) switch that receives an RF signal, and a nanoplasma DC switch that receives a DC bias voltage. The nanoplasma DC switch is positioned adjacent to but spaced apart from the nanoplasma RF switch. The nanoplasma DC switch induces a nanoplasma through the nanoplasma RF switch when the DC bias voltage is set to a first voltage level. By implementing the nanoplasma switching system in this manner, DC bias to turn on or off the nanoplasma RF switch can be realized without needing to use passive components such as DC blocking capacitors, choke inductors, or baluns for isolation.

Abstract: A device to convert a detected voltage, that is indicative of current conducted by a switching circuit, to a series of electrical pulses that is indicative of electrical power dissipated by the switching circuit responsive to the current. The device includes a transconductor circuit including a first circuit to receive a reference current and a first reference voltage, and to obtain a transconductance based on an auto-generated bias current and the reference current and the first reference voltage, where a value of the transconductance is determined by the reference current and the first reference voltage. The transconductor circuit further includes a second circuit coupled to the first circuit to receive the detected voltage, and to generate a first current based on the detected voltage and the obtained transconductance.

Abstract: Apparatus and methods for control and calibration of external oscillators are provided herein. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator that is external to the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.

Abstract: Systems, devices, and methods related to electrostatic discharge (ESD) protection in radio frequency (RF) switch circuitry are provided. An electrostatic discharge (ESD)-protected radio frequency (RF) switch circuitry includes a common port; at least one terminal port; a switch circuitry coupled between the common port and the at least one terminal port, wherein the switch circuitry comprises one or more transistors connected in a stacked configuration; and a first ESD protection circuitry coupled between a gate of a first transistor of the one or more transistors and a driver circuitry for the first transistor.