Abstract: An analog-to-digital (ADC) converter system and method of using the system that can be used in low power situations. The converter can periodically or recurrently turn off a reference standard in order to conserve power and instead using a stable supply source as a reference voltage. A precise conversion for signal from the analog to the digital domain while maintaining a low quiescent current.

Abstract: A three-phase power meter can monitor power on both 3-wire and 4-wire power lines. The power meter measures at least two voltages between phase conductors of the power line, and at least one voltage between a phase conductor and a neutral conductor of the power line when the neutral conductor is available. Using at least some of the measured voltages, the power meter can then operate in a first mode when coupled to a 3-wire power line to determine power on the power line based on the measured voltages, or operate in a second mode when coupled to a 4-wire power line to determine power on the power line based on the measured voltages.

Abstract: Packages for wireless temperature sensor nodes are described. These wireless temperature sensor nodes are suitable for sensing the temperature of remote objects, such as objects that are difficult to access. These packages are designed to enhance the sensor's ability to sense temperature. For example, these packages may be designed to provide a low thermal resistance path between the object and the temperature sensor, a high thermal resistance between an antenna of the wireless temperature sensor node and the object, and at least in some embodiments, immunity to vibrations. One such package includes means for providing a thermal conductive path from the temperature sensor to a thermally conductive support in contact with the object (for example with a thermal resistance less than 10 K/W), and means for thermally conductively decoupling the circuit board from the thermally conductive support (for example by at least 100 K/W).

Abstract: An automated testing system comprises a high side switch circuit coupled to an input/output (I/O) connection, a low side switch circuit coupled to the I/O connection, a high side force amplifier (HFA) coupled to the high side switch, a low side force amplifier (LFA) coupled to the low side switch, an adjusting circuit coupled to the HFA and the LFA, and a control circuit configured to change the adjusting circuit to change control of current at the I/O connection from one of the HFA or LFA to the other of the HFA or LFA.

Abstract: Aspects of this disclosure relate to one or more particles that move within a container in response to a magnetic field. A measurement circuit is configured to output an indication of the magnetic field based on position of the one or more particles.

Abstract: A memory device comprising a memory array including memory cells to store memory data, error correcting code (ECC) circuitry configured to generate ECC data and use the ECC data to detect errors in the memory data, and an ECC circuitry checker. The ECC circuitry checker is configured to substitute the ECC data with check ECC data, compare an output of the ECC circuitry to an expected output when the substituted check ECC data is applied to the ECC circuitry, and generate an alert when the comparing indicates an error in the ECC circuitry.

Abstract: A network interface module for coupling a host device to a switched network as a network node is described. The network interface module comprises a single half-duplex port for communicatively coupling to a shared bus of the switched network, at least one frame queue sized to store one multicast read frame received via the shared bus, and logic circuitry. The logic circuitry is configured to decode a read command for the interface module included in a payload of the multicast read frame that includes multiple read commands for other network nodes of the switched network, and transmit a response frame including read data on the shared bus when detecting the shared bus is available for transmitting.

Abstract: Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.

Abstract: The present disclosure enables firmware-based interleaved-ADC gain calibration and provides hardware-thresholding enhancements. An on-chip memory may store subADC samples and a microprocessor accesses these stored samples for use with the calibration algorithm. Power estimates may be performed using square of each subADC sample to estimate gain error. Thresholding may be applied to the subADC samples, such as Maximum Amplitude Thresholding, Minimum Power Thresholding, and/or using Histogram Output Memory, to determine that samples are valid and may be used for calibration or that subADC data are to be discarded and a new subADC data capture is to be started.

Abstract: The present disclosure provides a method of fabricating a target capture and sensor assembly. The method comprises the steps of: providing a fluid path with a target capture surface comprising an anchor species with a first functional group disposed thereon; providing a target capture species to the target capture surface of the fluid path, wherein each target capture species comprises a target capture part and a second functional group configured to react with the first functional group; and exposing at least a portion of the target capture surface of the fluid path to photo radiation so as to cause a photo-initiated reaction between the first functional group and the second functional group, wherein the target capture and sensor assembly further comprises a sensing surface in the fluid path and wherein the target capture surface and the sensing surface are in fluid communication with one another.

Abstract: Embodiments of the present invention provide improved fault detection and mitigation systems, methods, and techniques used in a BMS in an energy storage system (for example, grid energy storage). Embodiments of the present invention may detect battery malfunction in a battery stack and take quick corrective and preventative measures accordingly. Embodiments of the present invention may also provide select redundant components to implement safety techniques described herein.

Abstract: Herein disclosed are approaches for protecting sensitive information within a fingerprint authentication system that can be snooped and utilized to access the device, secured information, or a secured application. The approaches can utilize encryption keys and hash functions that are unique to the device in which the fingerprint authentication is being performed to protect the sensitive information that can be snooped.

Abstract: Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

Abstract: Microelectromechanical systems (MEMS) switches are disclosed. Parallel configurations of back-to-back MEMS switches are disclosed in some embodiments. An isolation connection of constant electrical potential may be made to a midpoint of the back-to-back switches. In some embodiments, a separate MEMS switch is provided as a shunt switch for the main MEMS switch. MEMS switch device configurations having multiple switchable signal paths each coupling a common input electrode to a respective output electrode are also disclosed. The MEMS switch device includes shunt switches each coupling a respective output electrode to a reference potential. The presence of a shunt switch coupled to an output electrode enhances the isolation of the signal path corresponding to that output electrode when the path is open.

Abstract: Digital isolators operable in multiple power modes are described. The digital isolators include a low power mode, in which some circuitry of the isolator operates in a lower power state than in other mode(s) of operation or may be deactivated, and in which data communication across the isolator is not permitted. The isolator may wake from the low power mode in response to a detected event or may periodically wake. Circuitry on one side of the isolator may dictate when and how the isolator wakes from a lower power mode.

Abstract: Impedance paths for integrated circuits having microelectromechanical systems (MEMS) switches that allow for electrical charge to bleed from circuit nodes to fixed electric potentials (e.g., ground) are described. Such paths are referred to herein as charge bleed circuits. The circuit nodes may be circuit locations where electrical charge may accumulate because there is no other path for the electrical charge to dissipate. In some embodiments, a charge bleed circuit includes a switchable device (e.g., a MEMS switch, a solid-state device switch, or a circuit including various solid-state device switches that, collectively, implement a device that can be switched on and off) that connects and disconnects the impedance path from a circuit node. This may allow the device to perform different types of measurements at desired performance levels.

Abstract: A rate of change of current sensor includes two measurement coils, arranged on a substrate or printed circuit board. The coils form loops and progress substantially around a target measurement conductor. This ensures that the two measurement coils both receive the same electrostatic coupling from external conductors which are not the target of the measurement operation. Further, the two measurement coils are arranged such that the first coil and the second coil are, on average, the same distance to the current-carrying conductor of interest.

Abstract: System in package (SiP) modules are compact packages that include components such as processors, memory, sensors, and passive components on a single substrate. One low cost and compact way to integrate an antenna into a SiP module is to suspend an antenna in molding compound so that the antenna is embedded in the real estate of the molding compound layer. To embed the antenna, the molding compound is first deposited. A cavity can be cut in the molding compound to hold the antenna. The cavity can be filled with conductive material to form the antenna. Further molding compound can be deposited to cover the antenna and enclose the antenna in the molding compound layer. Ground structures can also be suspended in the molding compound. Such an embedded antenna can be particularly useful for radio applications.

Abstract: Continuous-time (CT) analog-to-digital converters (ADCs) implementing digital correction of digital-to-analog converter (DAC) errors are disclosed. In a CT pipeline stage of a CT ADC, a CT analog input signal is sent to two different paths. A first path (a “feedforward” path) includes a cascade of a sub-ADC and a sub-DAC. A second path (a “forward” path) includes an analog delay circuit to align the delays of the input signal in the feedforward and forward paths. A combiner subtracts the output of the analog delay of the forward path from the output of the sub-DAC in the feedforward path to generate a residue signal. Devices and methods disclosed herein are based on recognition that, if the errors introduced by the sub-DAC are known, they can be corrected in the digital domain during reconstruction, achieving superior NSD and distortion performance compared to conventional approaches.

Abstract: Systems and methods related to communication interface are provided. An interface circuitry arrangement for communication between integrated circuit (IC) devices, the interface circuitry arrangement including serial peripheral interface (SPI) circuitry having an SPI clock port, an SPI data port, and an SPI chip select (CS) port; inter-integrated circuit (I2C) circuitry having an I2C clock port and an I2C data port, wherein the I2C clock port and the SPI clock port are electrically coupled to a first connection port, and wherein the I2C data port and the SPI data port are electrically coupled to a second connection port; pattern detection circuitry to detect a signal pattern at a third connection port, the third connection port electrically coupled to the SPI CS port; and selection circuitry to selectively couple the SPI circuitry or the I2C circuitry to a data path responsive to an output of the pattern detection circuitry.