Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter where the stage comprises a plurality of slices that can be operated together to form a composite output, can have reduced thermal noise, whilst each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance.

Abstract: A device for providing a reset signal to one or more sequential logic circuits in an electronic system responsive to a supply voltage condition includes a first voltage detector circuit to generate a first pulse after the supply voltage rises to a first threshold voltage level. The device further includes a second voltage detector circuit to generate a second pulse after the supply voltage falls below a second threshold voltage level. The device additionally includes a latch circuit to store a first value based on the first pulse after the supply voltage rises to the first threshold voltage level, disable the first voltage detector circuit after storing the first value, reset to store a second value based on the second pulse after the supply voltage falls below the second threshold voltage level, and to disable the second voltage detector circuit after the resetting.

Abstract: SPI frame for simultaneously entering 8 bit daisy-chain mode from 16 bit register addressable mode. Some products that implement SPI may be connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses. The whole chain acts as a communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Large latency occurs during the entry into daisy-chain mode which increases as a function of the number of linked SPI devices. A means for simultaneously instructing all connected devices to enter/enable daisy-chain mode is disclosed.

Abstract: Microelectromechanical systems (MEMS) switches are described. The MEMS switches can be actively opened and closed. The switch can include a beam coupled to an anchor on a substrate by one or more hinges. The beam, the hinges and the anchor may be made of the same material in some configurations. The switch can include electrodes, disposed on a surface of the substrate, for electrically controlling the orientation of the beam. The hinges may be thinner than the beam, resulting in the hinges being more flexible than the beam. In some configurations, the hinges are located within an opening in the beam. The hinges may extend in the same direction of the axis of rotation of the beam and/or in a direction perpendicular to the axis of rotation of the beam.

Abstract: Various transimpedance amplifier (TIA) arrangements for ultrasonic front-end receivers used in ultrasonic sensing applications are disclosed. An example TIA includes three common-source gain stages in a feedback loop with a common-gate stage. In some aspects, the TIA may include a level shifter configured to maintain the voltage at the gate of a transistor used to implement the first common-source gain stage of the feedback loop shifted by a certain amount with respect to the voltage at an input port to the TIA. In some aspects, at least portions of the TIA may be biased using bias currents that are configured to be process-, supply voltage-, and/or temperature-dependent. Various embodiments of the TIAs disclosed herein may benefit from one or more of the following advantages: reduced noise, reduced input impedance, reduced temperature coefficient of input impedance, and stability for a wide range of sensor frequencies.

Abstract: Disclosed herein are systems and methods for performing DC offset correction of a video signal received over an AC-coupled video link. In one aspect, a transmitter is configured to compute, and provide to a receiver, metadata indicative of a statistical characteristic (e.g., an average or a sum of values) for a group of active pixels of a video signal acquired by a camera. The receiver is configured to compute an analogous statistical characteristic on the video signal received over an AC-coupled video link, and to perform DC offset correction by modifying one or more values of the received video signal based on a comparison of the statistical characteristic computed by the receiver and the one computed by the transmitter and indicated by the received metadata.

Abstract: Disclosed herein are systems and techniques for content protection over synchronous data networks. For example, a method of communicating content protected data may include providing link synchronization information over a link of a synchronous bus, and providing content protected data over the link of the synchronous bus. The content protected data may be protected in accordance with the High-Bandwidth Digital Content Protection (HDCP) specification or the Digital Transmission Content Protection (DTCP) specification, for example.

Abstract: There is provided an active-pixel image sensor that uses a method of offsetting and interleaving to increase its resolution. In a basic configuration of the active-pixel image sensor, light from one optical transmitter is diffracted to create one diffraction pattern, and then light from another optical transmitter is diffracted to create another diffraction pattern. Light from further optical transmitters may also be diffracted to create further diffraction patterns sequentially after that. These diffraction patterns are offset from one another and then interleaved using time division multiplexing so as to create a single pixel output that has higher resolution than is feasible with an active-pixel image sensor that only utilizes one optical transmitter per pixel or that does not use diffraction patterns to create a larger field of view.

Abstract: The subject disclosure includes paralleling of monolithic embedded low drop-out (LDO) linear regulator power rails to provide additional load current, while maintaining accurate current sharing and balancing between the paralleled LDOs without additional power consumption for different load current requirements. Lossless current sensing is used to sense the current for each channel. An offset generator compares the voltages for a master channel and one or more slave channels, and generates an offset voltage according to the sensed error. The offset voltage is added between an input reference voltage and an output regulated voltage to cancel the offset of each channel, so the current of each channel is substantially the same. The lossless current sensing can be realized with equivalent series resistance compensation or current limit sensing. The offset generator can be realized with a resistor and current mirror topology or an input pair added to an error amplifier input.

Abstract: An electrochemical sensor is provided which may be formed using micromachining techniques commonly used in the manufacture of integrated circuits. This is achieved by forming microcapillaries in a silicon substrate and forming an opening in an insulating layer to allow environmental gases to reach through to the top side of the substrate. A porous electrode is printed on the top side of the insulating layer such that the electrode is formed in the opening in the insulating layer. The sensor also comprises at least one additional electrode. The electrolyte is then formed on top of the electrodes. A cap is formed over the electrodes and electrolyte. This arrangement may easily be produced using micromachining techniques.

Abstract: A power gating circuit includes a first transistor to couple a power supply to a gated power rail after receiving a control signal. The power gating circuit also includes two or more transistors coupled in parallel with the first switch, the one or more transistors configured to sequentially couple the power supply to the gated power rail according to a sequence determined by a comparator circuit and one or more cascaded latches.

Abstract: Disclosed herein are systems and methods for communicating video signals and control data over a HD, wired, AC-coupled video and control link. In one aspect, an example system includes a scheduler that is configured to allocate time slots for exchange of data between a transmitter and a receiver over such a link. The scheduler is configured to, for each of at least one or more video lines of a video frame of a video signal acquired by a camera, allocate a plurality of time slots for transmitting a plurality of video components of said video line from the transmitter to the receiver, allocate one or more time slots for transmitting transmitter control data from the transmitter to the receiver, and allocate one or more time slots for transmitting receiver control data from the receiver to the transmitter.

Abstract: The present disclosure provides a feedback control system and method for a bidirectional VCM. The system employs an analog core that is common to both the PWM and linear modes of operation. The analog core includes a feedback mechanism that determines the error in the current flowing through the motor. The feedback mechanism produces an error voltage that corresponds to the current error, and applies the voltage to a control driver. The control driver then controls the motor, based on the error voltage, in either a PWM or linear mode. By sharing a common core, the switching time between modes is improved. Furthermore, the output current error between modes is reduced.

Abstract: A common mode reference circuit comprises a divider stage and an output stage. The divider stage includes a first n-channel field effect transistor and p-channel filed effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node. The output stage includes a first FET connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and a common mode reference output at a series connection from the first FET to the second FET.

Abstract: Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a field effect transistor.

Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

Abstract: An integrated circuit is provided in which a surge protector, protecting against modest over-voltage events which may contain a lot of energy, and an electrostatic discharge (ESD) protector, protecting against high voltage events that may contain only a little energy, are provided within the integrated circuit package. The two types of protectors may protect against different types of electrical events.

Abstract: A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively “holds” or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.

Abstract: Accurately measuring bio-impedance is important for sensing properties of the body. Unfortunately, contact impedances can significantly degrade the accuracy of bio-impedance measurements. To address this issue, circuitry for implementing a four-wire impedance measurement can be configured to make multiple current measurements. The multiple current measurements set up a system of equations to allow the unknown bio-impedance and contact impedances to be derived. The result is an accurate bio-impedance measurement that is not negatively impacted by large contact impedances. Moreover, bad contacts with undesirably large impedances can be identified.

Abstract: Aspects of the embodiments are directed to a time-of-flight imaging system and methods of using the same. The time-of-flight imaging system includes a light emitter comprising at least one one-dimensional array of laser diodes; a photosensitive element for receiving reflected light from an object; and a light deflection device configured to deflect light from the light emitter to the object. In embodiments, the time-of-flight imaging system includes a lens structure to deflect emitting light from the laser diodes at a predetermined angle towards a light steering device.