Abstract: Systems and methods are provided for increasing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters. In some examples, systems and methods are provided for reducing total capacitance in an embedded excess loop delay compensation digital-to-analog converter (DAC) in a quantizer for a continuous time delta-sigma ADC. In other examples, the excess loop delay compensation DAC can be a current domain DAC, a charge domain DAC, or a voltage domain DAC. Additionally, methods are provided for digitally controlling the gain of an excess loop delay DAC. Furthermore, methods are provided to calibrate a gain mismatch between a main successive approximation register DAC and an excess loop delay DAC. The systems and methods provided herein improve performance of continuous time delta-sigma ADCs. Continuous time delta-sigma ADCs are high precision and power efficient ADCs, often used in audio playback devices and medical devices.

Abstract: Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.

Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.

Abstract: A light detection and ranging (LIDAR) system comprises a laser diode; a laser diode driver circuit configured generate a laser beam using the laser diode and to frequency chirp the generated laser beam according to a frequency chirp period; a laser splitter to split the generated laser beam into N transmit laser beams pointed at different angles, wherein N is an integer greater than one, and a frequency chirp period of each of the N transmit laser beams is the frequency chirp period of the generated laser beam; and multiple return beam paths to receive N return beams and determine time of flight values for the N return beams in parallel.

Abstract: Wideband baluns with enhanced amplitude and phase balance are provided. The wideband balun includes a first transmission line connected between a first port and a third port, and a second transmission line connected between a second port and a fourth port, and a third transmission line connected between the third port and a reference voltage, such as ground. To enhance phase and/or amplitude balance of the wideband balun, the wideband balun further includes a compensation structure operable to provide at least one of capacitive compensation or inductive compensation to balance the wideband balun. For example, in certain implementations, the compensation structure includes at least one of (i) a capacitor connected between the first port and the second port or (ii) a fourth transmission line connected between the first transmission line and the third port.

Abstract: Described herein are techniques of remotely performing key revocation on a device that cannot communicate outside of a local network of the device. The techniques involve including key revocation instructions in software update instructions that are sent to the device. The device may verify the software update instructions using one or more keys to determine whether they are safe for execution on the device. For example, the device may verify that the software update instructions have been sent by a trusted software provider. The device may execute the key revocation instructions included in the software update instruction to revoke use of a key of the key(s), and initiate use of a new key in place of the revoked key.

Abstract: Various examples are directed to a frequency-compensated amplifier circuit comprising a first multi-stage amplifier comprising a first amplifier input node, a first amplifier output node, and a first amplifier intermediate node. A first feedback path between the first amplifier input node and the first amplifier output node comprises a feedback resistance. A second feedback path between the first amplifier output node and the first amplifier intermediate node comprises a first capacitor and a portion of the feedback resistance. A first switch circuit may be electrically coupled to the first capacitor and to the feedback resistance. The first switch circuit may have a first state in which the first capacitor is coupled to a first tap point of the feedback resistance and the portion of the feedback resistance has a first value.

Abstract: One embodiment is a method for estimating an internal temperature of a battery, the method comprising obtaining multiple terminal impedance measurements, wherein each of the terminal impedance measurements is taken at a different one of a plurality of frequencies; determining model parameters for a multivariable polynomial regression model; and applying the multivariable polynomial regression model to the multiple terminal impedance measurements to estimate the internal temperature of the battery.

Abstract: Quadrature error correction (QEC) for radio transceivers are provided herein. In certain embodiments, a transceiver includes an in-phase (I) signal path including a first controllable amplifier coupled to a first data converter, and a quadrature-phase (Q) signal path including a second controllable amplifier coupled to a second data converter. The transceiver further includes a QEC circuit operable to correct for a quadrature error between the I signal path and the Q signal path by adjusting a gain of the first controllable amplifier and/or a gain of the second controllable amplifier.

Abstract: A structural electronics wireless sensor node is provided that includes layers of electronic components fabricated from patterned nanostructures embedded in an electrically conductive matrix. In some aspects, the structural electronics wireless sensor node includes a plurality of nanostructure layers that each form individual electronic components of the structural electronics wireless sensor node. In certain embodiments, the structural electronics wireless sensor node includes electronic components such as a resistor, a inductor, a capacitor, and/or an antenna.

Abstract: A microelectromechanical systems (MEMS) accelerometer is provided, comprising a substrate disposed in a plane defined by a first axis and a second axis perpendicular to the first axis; a first proof mass and a second proof mass coupled to the substrate and configured to translate in opposite directions of each other along a third axis perpendicular to the first and second axes; and at least one lever coupling the first proof mass to the second proof mass, wherein, the MEMS accelerometer is configured to detect acceleration along the third axis via detection of translation of the first and second proof masses along the third axis; and the MEMS accelerometer exhibits symmetry about the first and second axes.

Abstract: A contactless charging drawer for smart garments using magnetic coupling links. A frame with a primary coil creates a magnetic field which couples with a secondary coil disposed a drawer. Smart garments, or any device, can then be safely charged in the drawer. The combination provides for a wireless power charging environment while adding an extra degree of freedom in impedance transformation without the need for electrical contacts to the drawer.

Abstract: A device to predict failure in a power supply includes a converter circuit configured to generate a regulated output voltage. The device additionally includes a first feedback circuit to generate a first feedback voltage proportional to the regulated output voltage and a second feedback circuit to generate a second feedback voltage based on the regulated output voltage. The second feedback circuit includes a voltage sampling circuit to detect the regulated output voltage, a correction circuit to generate a correction signal responsive to a voltage difference between the regulated output voltage and a specified output voltage, a reference circuit to obtain a specified correction signal to apply to the power supply, a comparator circuit to determine whether a difference between the generated correction signal and the specified correction signal exceeds a threshold signal value, and an alerting circuit to generate an alert signal responsive to the determination.

Abstract: One embodiment is a microelectronic assembly including an assembly support structure; a first die including a pair of hot via comprising through-substrate-via (TSVs) extending through the first die between first and second sides thereof and a plurality of ground vias surrounding the pair of hot vias and extending through the first die between the first and second sides thereof. The first die further includes a pair of signal interconnect structures electrically connected to the pair of hot vias disposed on the second side of the first die. The assembly further includes a second die between the assembly support structure and the first die the pair of signal interconnect structures disposed on the first side thereof. The first die is connected to the second die via a signal die-to-die (DTD) interconnect structure including the signal interconnect structures of the first and second dies.

Abstract: Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions are provided herein. In certain implementations, a stacked thyristor protection structure with a high holding voltage includes a protection device having a trigger voltage and a holding voltage. A trigger voltage of the stacked thyristor protection structure is substantially equal to the trigger voltage of the protection device. The stacked thyristor protection structure further includes at least one resistive thyristor electrically connected to the protection device and operable to increase a holding voltage of the stacked thyristor protection structure relative to the holding voltage of the protection device. The at least one resistive thyristor comprising a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and a conductor connecting a collector of the PNP bipolar transistor to a collector of the NPN bipolar transistor.

Abstract: Customizable tunable filters are provided herein. In certain implementations, a tunable filter including: a first filter bank including a plurality of high-pass filters each having a different cutoff frequency, and a second filter bank including a plurality of low-pass filters each having a different cutoff frequency. The tunable filter further includes a first pair of switches configured to select a first filter chosen from the first filter bank, and a second pair of switches configured to select a second filter chosen from the second filter bank. The tunable filter operates with a first cutoff frequency of the first filter and with a second cutoff frequency of the second filter.

Abstract: A semiconductor device having a back-side field plate includes a buffer layer that includes a first compound semiconductor material, where the buffer layer is epitaxial to a crystalline substrate. The semiconductor device also includes field plate layer that is disposed on a surface of the buffer layer. The semiconductor device further includes a first channel layer disposed over the field plate layer, where the first channel layer includes the first compound semiconductor material. The semiconductor device further includes a region comprising a two-dimensional electron gas, where the two-dimensional electron gas is formed at an interface between the first channel layer and a second channel layer. The semiconductor device additionally includes a back-side field plate that is formed by a region of the field plate layer and is electrically isolated from other regions of the field plate layer.

Abstract: Various embodiments relate to an electrical feedthrough assembly an elongate conductor and a collar at least partially surrounding the elongate conductor along a portion of a length of the elongate conductor. The collar can be composed of a material having a thermal conductivity of at least 170 W/(m-K). A shell can be disposed around the collar. At one or more operating frequencies, at least a portion of a length of the electrical feedthrough assembly can be selected to provide at least one quarter wave transform.

Abstract: Microelectromechanical system (MEMS) inertial sensors exhibiting reduced parasitic capacitance are described. The reduction in the parasitic capacitance may be achieved by forming localized regions of thick dielectric material. These localized regions may be formed inside trenches. Formation of trenches enables an increase in the vertical separation between a sense capacitor and the substrate, thereby reducing the parasitic capacitance in this region. The stationary electrode of the sense capacitor may be placed between the proof mass and the trench. The trench may be filled with a dielectric material. Part of the trench may be filled with air, in some circumstances, thereby further reducing the parasitic capacitance. These MEMS inertial sensors may serve, among other types of inertial sensors, as accelerometers and/or gyroscopes. Fabrication of these trenches may involve lateral oxidation, whereby columns of semiconductor material are oxidized.

Abstract: A semiconductor die with high-voltage tolerant electrical overstress circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor includes a first thyristor and a resistive thyristor electrically connected in a stack between the signal pad and the ground pad, which enhances the holding voltage of the circuit relatively to an implementation with only the thyristor. Further, the resistive thyristor includes a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This allows the resistive thyristor to exhibit both thyristor characteristics and resistive characteristics based on a level of current flow.