Abstract: Microelectromechanical system (MEMS) inertial sensors exhibiting reduced parasitic capacitance are described. The reduction in the parasitic capacitance may be achieved by forming localized regions of thick dielectric material. These localized regions may be formed inside trenches. Formation of trenches enables an increase in the vertical separation between a sense capacitor and the substrate, thereby reducing the parasitic capacitance in this region. The stationary electrode of the sense capacitor may be placed between the proof mass and the trench. The trench may be filled with a dielectric material. Part of the trench may be filled with air, in some circumstances, thereby further reducing the parasitic capacitance. These MEMS inertial sensors may serve, among other types of inertial sensors, as accelerometers and/or gyroscopes. Fabrication of these trenches may involve lateral oxidation, whereby columns of semiconductor material are oxidized.

Abstract: This disclosure describes techniques to control switching operations of a switching regulator. The disclosure includes a system comprising a switching regulator configured to use an inductor to generate an output voltage signal from a. pulse-width-modulated (PWM) signal by controlling one or more switches of the switching regulator that vary charging operations of the inductor; transient handling circuitry coupled to receive a feedback voltage based on the output voltage signal and configured to generate first and second current signals that represent a difference between the feedback voltage and a reference voltage; and control circuitry configured to generate the PWM signal based on the first and second current signals such that the first current signal changes a frequency of an oscillator used to generate the PWM signal and the second current signal changes a bandwidth of a feedback loop associated with the switching regulator.

Abstract: One embodiment is a reconfigurable mixer topology for selectively implementing one of a harmonic rejection mixer (HRM) and a subharmonic mixer (SHM), the reconfigurable mixer topology comprising a mixer core comprising a plurality of differential mixers each having a first clock input and a second clock input; a clock generator for generating a plurality of clock signals each having a different phase; and a clock distributor for distributing the plurality of clock signals to the first and second clock inputs of the differential mixers in accordance with a designated operation of the reconfigurable mixer as an HRM or an SHM.

Abstract: Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

Abstract: This disclosure describes techniques to provide a regulator circuit using a component-on-top (CoP) package. The CoP package comprising a system-in-package (SIP) comprising regulator circuitry, the SIP having a top portion and a first side portion; and an inductor on the top portion of the SIP, wherein: the inductor is coupled to the regulator circuitry via the top portion of the SIP; and a first end of the inductor extends beyond the first side portion of the SIP.

Abstract: Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

Abstract: Thermal temperature sensors for power amplifiers are provided herein. In certain implementations, a semiconductor die includes a compound semiconductor substrate, and a power amplifier including a plurality of field-effect transistors (FETs) configured to amplify a radio frequency (RF) signal. The plurality of FETs are arranged on the compound semiconductor substrate as a transistor array. The semiconductor die further includes a semiconductor resistor configured to generate a signal indicative of a temperature of the transistor array. The semiconductor resistor is located adjacent to one end of the transistor array.

Abstract: An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.

Abstract: A pin driver control system for enhancing pulse fidelity can include a first current switch circuit with a current input node and a voltage input node, wherein the first current switch circuit provides a switched output current signal in response to a voltage control signal at the voltage input node. The system can further include a first current source configured to receive a bias control signal and, in response, provide a drive current signal to the current input node of the first current switch. The drive current signal can have a magnitude that exceeds a magnitude of the switched output current signal. The system can further include a bias control circuit configured to receive information about a desired bias current magnitude for use by the first current switch circuit and, in response, provide the bias control signal to the first current source.

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Abstract: Described herein are techniques for a system to track usage of a software application on a remote device, without having connectivity to the remote device. The system transmits an activation token to a computing device different from the remote device to activate the software application, and receives a deactivation token generated by the remote device from the computing device when the software application is deactivated. The system uses transmission of an activation token and receipt of a deactivation token as indicators of start and end times of use of the software application. For example, the system uses the indicated start and end times to determine a billing period for use of the software application.

Abstract: According to some aspects, there is provided a microelectromechanical systems (MEMS) device wherein one or more components of the MEMS device exhibit attenuated motion relative to one or more other moving components. The MEMS device may comprise a substrate; a proof mass coupled to the substrate and configured to move along a resonator axis; and a first shuttle coupled to the proof mass and comprising one of a drive structure configured to drive the proof mass along the resonator axis or a sense structure configured to move along a second axis substantially perpendicular to the resonator axis in response to motion of the proof mass along the resonator axis, wherein displacement of at least a first portion of the proof mass is attenuated relative to displacement of the first shuttle and/or a second portion of the proof mass.

Abstract: Columnar multi-axis microelectromechanical systems (MEMS) devices (such as gyroscopes) balanced against undesired linear and angular vibration are described herein. In some embodiments, the columnar MEMS device may comprise at least two multiple-mass columns, each having at least three proof masses and being configured to sense rotation about a respective axis. The motion and mass of the proof masses may be controlled to achieve linear and rotational balancing of the MEMS device. The columnar MEMS device may further comprise one or more modular drive structures disposed alongside each multiple-mass column to facilitate displacement of the proof masses of a respective column. The MEMS devices described herein may be used to sense roll, yaw, and pitch angular rates.

Abstract: Z-axis teeter-totter accelerometers with embedded movable structures are disclosed. The teeter-totter accelerometer may include an embedded mass which pivots or translates out-of-plane from the teeter-totter beam. The pivoting or translating embedded mass may be positioned to increase the sensitivity of the z-axis accelerometer by providing greater z-axis displacement than the teeter-totter beam itself exhibits.

Abstract: Aspects of the present disclosure provide miniaturized isolator modules capable of transferring power and/or data signals across an isolation barrier by way of a transformer while maintaining intrinsic safety (IS) compliance. For example, the isolator modules may provide power from a non-IS side to an IS side of the isolation barrier while protecting the IS side in the event of an overvoltage and/or overcurrent event on the non-IS side. In some aspects, an isolator module includes one or more silicon protection devices, which facilitate the miniaturization of the isolator module while maintaining protection against overvoltage and/or overcurrent events in accordance with IS standards. In some aspects, an isolator module includes a transformer adapted for IS compliance. For example, coils of the transformer may be disposed on opposing sides of an isolation barrier having a thickness of at least 200 microns.

Abstract: Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output.

Abstract: Amplifiers with wide input range and low input capacitance are provided. In certain embodiments, an amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and/or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to decouple the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to decouple the input terminals from the p-type input transistors when unused.

Abstract: Systems and methods for a power-efficient 3-level digital-to-analog converter. A converter cell using a current starving technique keeps a portion of the converter cell turned on in a low power mode, as opposed to completely turning off current in selected modes. A conversion system keeps a first set of converters active while allowing a second set of converters to be powered down. Systems and methods presented save power and allow for efficient reactivation of converters.

Abstract: Systems and methods are provided for a distributed mufti-sensor witness integrity sensing platform (WISP) approach which allows for positioning of sensors in an enclosed space. In particular, a WISP platform is divided into two modules, with a base module is connected to multiple edge sensor modules with a wired connection. In general, splitting up the distributed WISP system described herein allows multiple sensors to be placed in an enclosed (and generally inaccessible) location. The senor data can be transmitted from the multiple edge sensor modules via a connection to the base module. Additionally, the use of the two module system as provided herein allows the sensors to be positioned meters away from the first module.

Abstract: Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided a for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other I-DACs. Techniques are disclosed for decreasing mismatch among multiple I-DACs while improving efficiency of rotational dynamic element matching.