Abstract: A high speed program tracer providing compression using linear increment run length values, displacement values corresponding to discontinuities, and loop compression. A program count sequencer receives program count values from a processor, and outputs various program count values and signals to allow compression calculations to be made based upon linear increment run lengths, discontinuity detection, and detection of repeating instruction loops. Compression may be achieved using selected numbers of words to represent various compression values.

Abstract: A switched current temperature sensing circuit comprises a BJT arranged to conduct a forced emitter current IE of the form Ifixed+(Ifixed/?), such that the base current is given by Ifixed/? and the collector current is given by Ifixed+(Ifixed/?)?(Ifixed/?)=Ifixed. Base current Ifixed/? is mirrored to the emitter, and a current source provides current Ifixed, which is switched between at least a first value I and a second value N*I such that the BJT's base-emitter voltage has a first value Vbe1 when Ifixed=I and a second value Vbe2 when Ifixed=N*I, such that: ?Vbe12=Vbe1?Vbe2=(nFkT/q)(ln N), where nF is the BJT's emission coefficient, k is Boltzmann's constant, T is absolute temperature, and q is the electron charge.

Abstract: Reference signal generators are provided that automatically adjusts a reference signal's amplitude when that signal is delivered into system loads having unknown capacitances. The amplitude is preferably initiated at a maximum amplitude to insure operation of system elements that require the reference signal. It is subsequently adjusted downward to a controlled reference amplitude which is predetermined to be an amplitude sufficient to sustain proper operation of the system elements but sufficiently reduced to minimize the spurious signals typically generated by fast high-level current transitions. In addition, the reduction to the controlled amplitude reduces the system current drain. The level control is realized in a buffer amplifier so that the amplitude level of an oscillator signal can be set independently to maximize its signal-to-noise performance. Accordingly, requirements for the reference amplitude do not compromise requirements for the amplitude level of the oscillator signal.

Abstract: A semi-fusible link system and method for a multi-layer integrated circuit including active circuitry on a first layer having a metal one layer including a semi-fusible link element on a second layer having a metal two layer adapted for interconnecting with the metal one layer, and a selector circuit disposed on the first layer.

Abstract: A current-mode instrumentation amplifier (IA) includes first and second buffer amplifiers which receive a differential voltage (VINP?VINN) and provide output voltages at respective output nodes; a resistance R1 is connected between the nodes and conducts a current IR1 that varies with VINP?VINN. In one embodiment, each amplifier includes a transistor connected in series with R1 which conducts current IR1; these currents are coupled to the input and output terminals of a current mirror, preferably via respective virtual ground nodes such that the IA requires only one current mirror, to produce the IA's output voltage. To minimize DC mismatch errors, the IA is chopper-stabilized, with the buffer amplifiers and signal current paths chopped using a two-phase chopping cycle.

Abstract: A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage, without having to generate the reference voltage, by using charge redistribution. The switched-capacitor circuit prevents the need to dissipate power while producing the reference voltage. The switched-capacitor circuit is coupled to a comparator and to a logic circuit which provides control signals for switching. The switched-capacitor circuit comprises a plurality of capacitors arranged according to several embodiments.

Abstract: In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).

Abstract: A MEMS inertial sensor is secured within a premolded-type package formed, at least in part, from a low moisture permeable molding material. Consequently, such a motion detector should be capable of being produced more economically than those using ceramic packages. To those ends, the package has at least one wall (having a low moisture permeability) extending from a leadframe to form a cavity, and an isolator (with a top surface) within the cavity. The MEMS inertial sensor has a movable structure suspended above a substrate having a bottom surface. The substrate bottom surface is secured to the isolator top surface at a contact area. In illustrative embodiments, the contact area is less than the surface area of the bottom surface of the substrate. Accordingly, the isolator forms a space between at least a portion of the bottom substrate surface and the package. This space thus is free of the isolator.

Abstract: A dual-mode delta-sigma analog to digital converter system is disclosed that uses a feed forward modulator and includes a low frequency resonator circuit and a high frequency resonator circuit and includes a feed-forward path from the final integrator in the high-frequency resonator circuit to a summer. The digital converter system includes a selection unit for permitting the high frequency resonator circuit and the low frequency resonator circuit to be employed in a first mode of operation. The system also permits the high frequency resonator circuit and the feed-forward path from the final integrator in the high-frequency resonator circuit to the summer to be disabled in a second mode of operation.

Abstract: A method is disclosed for decoding a coded input stream and producing a decoded output stream. The method includes the steps of assigning each successive code in the input stream a dictionary definition that references a location in an output stream, and providing literal codes and reference codes to an output memory such that the reference codes include a source address in the output stream and a length of a code at the source address.

Abstract: A chopper-stabilized current mirror includes a pair of FETs connected to mirror an input current Iin. In one embodiment, switching networks S1 and S2 have their respective inputs connected to the FETs' drains, and are operated with clock signals CLK1 and CLK2, respectively. An ro boost amplifier A1 has its inputs connected to the outputs of S2 and its outputs connected to the gates of a pair of cascode FETs via a switching network S3 which is operated with clock signal CLK2S, with the drain of one cascode FET connected to Iin and the drain of the other providing the mirror's output Iout. S1 is clocked to reduce mismatch errors and S2 and S3 are clocked to reduce errors due to A1's offset voltage, with CLK2 and CLK2S shifted with respect to CLK1 to reduce errors due to parasitic capacitances.

Abstract: A three-dimensional integrated capacitance structure comprises at least two arrays of “unit cells” on respective layers of an IC, with each unit cell comprising a center conductor and a conducting ring which surrounds the center conductor. Each array comprises a plurality of unit cells, tiled on a given IC layer at a predetermined pitch. The arrays are arranged vertically such that adjacent vertical arrays are offset in the x and y dimensions by a predetermined fraction—preferably ½—of the unit cells' pitch. The structure includes vias arranged to interconnect the arrays such that each center conductor is connected to a conducting ring of the array immediately above and/or below the center conductor, and such that each conducting ring is connected to a center conductor of the array immediately above and/or below the conducting ring.

Abstract: A current mirror circuit includes a current input node for receiving an input current, an upper, cascoded current mirror, a lower current mirror, and a biasing means. In a FET implementation, the upper mirror includes first and second cascoded FETs which are connected together at the current input node, and third and fourth cascoded FETs connected to mirror the current conducted by the first and second FETs. The lower current mirror receives the mirrored current and mirrors it back to the upper mirror, thereby providing positive feedback. The net loop gain is between zero and one. When so arranged, the third and fourth FETs conduct a current which is proportional to an applied input current. The upper mirror transistors are biased such that the voltage at the current input node is substantially closer to the supply voltage than the voltages at the gates of the first and third FETs.

Abstract: Methods and apparatus are provided for encoding data.

Abstract: A digital baseband processor is provided which receives a system clock generated by a system oscillator and generates a plurality of clock signals from the system clock. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and other modules which may require one of the plurality of clock signals for operation. The digital baseband processor also includes a power management circuit which may power down the system oscillator when modules such as the digital signal processor and microcontroller do not require clock signals derived from the system oscillator. The power management circuit may gate off clock signals to modules when those modules do not require clock signals, without powering down the system oscillator.

Abstract: A semiconductor substrate (1) comprises first and second silicon wafers (2,3) directly bonded together with interfacial oxide and interfacial stresses minimised along a bond interface (5), which is defined by bond faces (7) of the first and second wafers (2,3). Interfacial oxide is minimised by selecting the first and second wafers (2,3) to be of relatively low oxygen content, well below the limit of solid solubility of oxygen in the wafers. In order to minimise interfacial stresses, the first and second wafers are selected to have respective different crystal plane orientations. The bond faces (7) of the first and second wafers (2,3) are polished and cleaned, and are subsequently dried in a nitrogen atmosphere. Immediately upon being dried, the bond faces (7) of the first and second wafers (2,3) are abutted together and the wafers (2,3) are subjected to a preliminary anneal at a temperature of at least 400° C. for a time period of a few hours.

Abstract: Structures and methods are provided for generating a digital display signal from an analog signal that is limited to 2N discrete analog levels and from a synchronization signal that defines spatial order for the digital display signal. These structures and methods accurately synchronize digitizers to the analog signal and they follow from a recognition that enhanced digitizer resolution will generate code patterns which easily distinguish between correct and incorrect sampling of the analog signals. Accordingly, the digitizers quantize the analog samples into an M-bit digital display signal wherein M exceeds N.

Abstract: In one embodiment, a trace buffer circuit for use with a pipelined digital signal processor (DSP) may include a series of interconnected registers that operate as a first-in first-out (FIFO) register on a write operation and a last-in first-out (LIFO) register on a read operation. On the write operation, a branch target/source address pair may be written to a first pair of trace buffer registers and, the contents of each register may be shifted two registers downstream. On the read operation, one instruction address may be read from a top register, and the contents of each register may be shifted one register upstream. The trace buffer may also include structure to enable compression of hardware and software loops in the program flow. A valid bit may be assigned to each instruction address in the trace buffer and a valid bit buffer with a structure parallel to that of the trace buffer may be provided to track the valid bits.

Abstract: Plural sum of absolute difference devices are used to calculate distortions between specified parts of specified images in a video stream. The video can be from a video camera, or other device.

Abstract: A flip around amplifier circuit is provided that includes an amplifier having first and second amplification stages, a Miller capacitor, and a resistive element in series with the Miller capacitor, where an output line of the second amplification stage can be coupled to an output line of the first amplification stage through the Miller capacitor and the series resistive element. The circuit can include a feedback capacitor having a first plate coupled to an input line of the amplifier, and a flip around switch that can be operated so as to connect an output line of the amplifier to a second plate of the feedback capacitor. The circuit's classical transfer function can include a zero associated with the Miller capacitor and the series resistive element, and a pole associated with the feedback capacitor and the on-resistance of the flip around switch, where the zero is substantially equal to the pole.