Abstract: A multi-bit sigma-delta analog-to-digital converter (ADC) has a single-ended input for receiving an analog input signal. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a multibit digital feedback signal from a Flash ADC. The feedback current is summed with the input signal with the feedback current. The summed signal is integrated on a continuous-time basis. The IDAC is selectively connectable to the summing node via a first path and a second path. The first path transmits current from the IDAC to the summing node with a first polarity and the second path transmits current from the IDAC to the summing node with an inverted polarity. This can reduce flicker noise and can allow the converter to operate without any mid-scale biasing current sources.

Abstract: A communication system includes a master device which communicates with a chain of serially-connected slave devices. The master originates messages, each of which is intended for a particular ‘target’ slave device. Each message contains a ‘distance to target device’ value equal to the number of devices between the master and target, and a data packet containing data to be conveyed between the master and target. Each slave device determines if the ‘distance to target device’ value indicates that it is the target. If not, the slave device increments or decrements the value in real time, with no latency, and transmits the modified message to the next slave device until received by the target device. In one embodiment, the target device may place data in the data packet, and the slave devices are arranged to buffer the data back to the master device.

Abstract: A memory having multiple locations for data storage is updated by performing the following method. The memory locations are grouped into commonly accessible groups of one or more data locations. First, a control array is provided. The control array is associated with a predetermined type of memory update operation, and has a local indicator for each commonly accessible group of memory locations respectively. Next, the instruction stream to the memory is monitored to determine the current memory operation type, and the set of groups of memory locations upon which the current operation is to be performed. If the current memory operation is an operation of the predetermined type, the control array is updated. If the current operation is an operation other than the predetermined type, the state of the respective local indicator of each group of the set is determined. The current operation is then performed upon each group in the set in accordance with the state of its respective local indicator.

Abstract: The invention provides a sensor element formed in a first substrate and having a thermal barrier disposed between the sensor element and a heat source provided elsewhere on the first substrate. The thermal barrier includes at least one pair of trenches formed within the first substrate, individual trenches of the pair being separated by a cavity.

Abstract: A switching circuit comprising: first and second steering switches operable to make or break a path between first and second terminals thereof, and each steering switch further having a control terminal for controlling the switch, the first and second steering switches having their control terminals driven by first and second switching signals, the first and second switching signals having a first frequency and the second switching signal being in anti-phase with the first switching signal and a first chopping switch operable to make or break a path between first and second terminals thereof and being connected in series with at least one of the first and second steering switches and receiving at its first terminal an input to be modulated, wherein the control terminal of the chopping switch is driven by a first switching control signal such that the chopping switch is non-conducting while the first and second steering switches are changing between being conducting and being non-conducting.

Abstract: A MEMS switch has 1) a first contact, and 2) a second contact that is movable relative to the first contact. At least one of the contacts is electrically conductive and has a platinum-series based material.

Abstract: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.

Abstract: Signal sampler embodiments are provided for processing input signals along signal paths in response to mode-command signals. They include a follower transistor with a control terminal and a current terminal that establish at least part of a signal path. They also include a switched-capacitor network that receives signals from the current terminal in response to a first mode-command signal and that couple a selected one of a set of reference signals to the current terminal in response to a second mode-command signal. During a second mode-command signal, a bias switch is arranged to bias off the follower transistor by coupling a bias signal to the control terminal that approximates the selected reference signal. Accordingly, the amplitude of the reference signals can be increased to facilitate an increased dynamic range of the input signals without biasing the follower transistor into breakdown.

Abstract: A memory cell includes: a charge storage element (e.g., capacitor); a switch constructed and arranged to selectively connect the charge storage element to a first data line, responsive to a first select signal; and a gain element having an input connected to receive a signal from the capacitor and constructed and arranged to selectively provide a corresponding output signal to a second data line, responsive to a second select signal. The switch can be a FET having a drain connected to the first data line, a source connected to the capacitor and a gate connected to the first select signal. The gain element can be a FET having a gate connected to the capacitor, a source connected to the second data line and a drain selectively connected to one of an upper power supply and a lower power supply. The switch can transfer a signal from the first data line onto the capacitor and can transfer a signal from the capacitor onto the first data line when selected by the first select signal.

Abstract: The invention provides a sensor array having a plurality of sensor elements formed in a first substrate and having a plurality of die temperature sensors located thereabout. Each of the die temperature sensors are configured to provide an output related to the temperature of the die on which they are located, the sensor elements providing an output indicative of the intensity of radiation incident thereon.

Abstract: An analog to digital converter is provided comprising an array of capacitors for sampling an input, each capacitor having at least one associated switch for controllably connecting a terminal of the capacitor to a first reference voltage or to a second reference voltage; and a sequence generator for generating a sequence of bits, wherein during sampling of the input onto the array of capacitors an output of the sequence generator is supplied to the switches of a first group of capacitors to control whether a given capacitor within the first group is connected by its associated switch to the first reference voltage or to the second reference voltage.

Abstract: A method of operating a digital to analog converter comprising the steps of operating the converter in a first mode to obtain a first conversion result, operating the converter in a correction mode in which one or more correction conversions are made, and wherein each correction conversion takes the result of a preceding result as a valid starting point.

Abstract: Each of a number of resonator masses is split into two separate lobes or masses joined together by a short flexure. The short flexure allows the separate lobes or masses to rotate slightly as they resonate so as to substantially relieve longitudinal stresses in certain resonator structures.

Abstract: An optical modulator structure includes a block that includes electro-optical (EO) materials. A waveguide and electrode structure is formed on a substrate. The block is in close proximity to the waveguide and electrode structure so as to form optical modulation when electric fields in the block are varied.

Abstract: Generators are provided for supplying reference signals that are especially suited to signal conditioning systems such as analog-to-digital converters. They generate reference signals with low output impedances that reduce spurious signals and shorten recovery times. Filters are included to decouple reference structures and thereby reduce noise signals, reduce ringing and dampen resonant circuits that may be formed with the inductance of bond wires and various parasitic chip capacitances. The generators are configured to provide this high performance with a reduced current consumption.

Abstract: A mode coupler structure includes a discriminating structure that discriminates between various incoming modes from an input optical fiber structure. A waveguide structure is coupled to the discriminating structure that couples light not discriminated by the discriminating structure to an output optical fiber structure.

Abstract: An output stage interface circuit (1) comprises a main bipolar transistor (Q1) coupling a data output terminal (5) to a first rail (2) to which the positive of the power supply voltage (VDD) is applied, and a substrate diffusion isolated main NMOS transistor (MN1) coupling the data output terminal (5) to a second rail (3) which is held at ground. Control signals from a data control circuit (6) selectively operate the main bipolar transistor (Q1) and the main MOS transistor (MN1) for determining the logic high and low states of the data output terminal (5) during data output.

Abstract: The invention provides a bandgap voltage reference circuit that is adapted to provide a ?Vbe of sufficiently large value that no amplification is required, and therefore any offset contribution is not gained. Using a stacked arrangement of three pairs of transistors, the invention reduces the requirement for multiple resistors within a circuit and can therefore minimise errors due to resistor matching and value. Internally provided circuitry for reducing voltage curvature is provided with the result that a circuit having low offset sensitivity and curvature correction is provided.

Abstract: A line interface performs echo cancellation without the use of a hybrid filter network and includes a transmit path having a line driver, a single matching network terminating the line, and a single transformer. The transformer uses split windings on both the primary side and the secondary (line) side. Each half of the primary side is tapped to obtain a turns ratio of N1:N2, while each half of the secondary side of the transformer has N windings. The single matching impedance is coupled in parallel between the first winding and the second winding on each half of the primary side. Either the voltage across the matching impedance or the voltage across the receive terminals is bootstrapped to the receive signal through multiple negative feedbacks. The transfer function of the line driver is shaped as a first-order high-pass filter (HPF) to reject any out-of-band noise and distortion components.

Abstract: The invention provides a method of processing a sequence of operands to produce compiled code for a target data processor, the method comprising the steps of: automatically analysing a source code to produce a fist representation of that code in single static assignment form; transforming the first representation into a second representation by unlooping ? nodes within the single static assignment form so as to create code suitable for tree pattern matching to be performed thereon; performing tree pattern matching on the second representation of the code; and re-looping the ? nodes.