Abstract: A micromachined device is provided that establishes select dimensional relationships between micromachined structures to achieve correlation in dimensional variation among these structures. Such dimensional relationships are achieved through consistent spacing between desired operating structures and by adding new structures (i.e., dimensional control structures) which provide additional consistent spacing at desired locations within the micromachined device.

Abstract: Acoustic signals received by the ears are controlled by feeding back and filtering the signal to be applied to the speaker, rather than by use of a feedforward filter. The feedback filter may incorporate an electrical model of the speaker-to-ear transfer function to force the ear signals to a desired ratio of amplitudes and phases as a function of the frequency. The signals to be output to the right and left channels are fed back through a filter to obtain a feedback signal. The feedback signal is subtracted from one input channel and added to the other input channel to provide the output signals. This technique may be used both in stereo spreading and in three-dimensional localization of a monaural sound source. By using feedback instead of feedforward, the system can be readily adapted to different playback environments. Through a simple adjustment of the electrical model of the speaker-to-ear transfer functions, this system automatically provides the desired ear signals.

Abstract: A sampling capacitor interface circuit for storing charge on a sampling capacitor related to a sample of an input signal voltage during a charging phase and to transfer the stored charge to an output during a charge transfer phase, such input signal having bipolar voltages within a range above and below an input signal common mode voltage. The interface circuit includes a transistor having: an input electrode fed by the input signal; an output electrode coupled to the sampling capacitor; and, a control electrode. A controller is provided for producing a control signal having a first voltage during the charging phase and a second voltage during the charge transfer phase, such voltages being a unipolar voltage referenced to the input signal common mode voltage.

Abstract: A differential line driver having a pair of transistors arranged as a differential pair for driving a transmission line with a differential logic output signal produced in accordance with a differential logic input signal fed to the base electrodes of the pair of transistors. The differential line driver includes circuitry for suppressing EMI emissions generated by common mode voltage switching transients produced at the collector electrodes of the pair of transistors in response to changes in the differential logic input signal. The common mode voltage switching transient suppression circuitry includes a pair of additional transistors. The differential logic input signal is fed to base electrodes of the additional transistors, and through such additional transistors, to the base electrodes of the pair of transistors of the differential pair. In one embodiment of the invention, the additional transistors are connected in a Darlington pair arrangement with the pair of transistors of the differential pair.

Abstract: A high impedance node of a transimpedance stage drives the input of a unity-gain forward buffer. A unity-gain integrated back-buffer is enabled to drive the high-impedance node from the output of the forward buffer when the forward buffer is disabled. A voltage from the forward buffer limits the reverse-biasing of all transistors in the back-buffer when the back buffer is disabled, and a voltage from the back-buffer limits the reverse-biasing of all transistors in the forward buffer when the forward buffer is disabled. The output-driver transistors of the forward buffer are bootstrapped to the output voltage through resistors which, when the forward buffer is enabled, bias pre-driver transistor coupled to the output-driver transistors. Neither the forward buffer nor the back-buffer consume a significant amount of power when not enabled.

Abstract: A comb filter for use in a video decoder is described. The comb filter includes a line memory for storing as successive pairs of U and V samples of a decoded video signal corresponding to a previous horizontal line of video information and a line memory for storing a second previous horizontal line of video information. The filter also includes a circuit to calculate an average value of both U and V from a previous sample and a corresponding sample from a previous line. The filter also includes a circuit for calculating a correction term for each one of the averages. The correction term is calculated from the opposite color component as was used to calculate the average value.

Abstract: A micromachined device has a plurality of rotationally dithered masses that are used to sense acceleration. To eliminate common modes, the masses are dithered in an equal and opposite manner. To help maintain this relationship between the movement of the masses, a coupling fork provides minimal resistance to anti-phase movement and substantial resistance to in-phase movement. Electrodes are used to detect changes in capacitance between the masses and the substrate resulting from rotation of the device about a radial axis of a mass. These electrodes are electrically connected to eliminate gradients that are caused by external forces and manufacturing differences. Four masses or more can be provided, arranged in a two-dimensional array, such as a square or hexagon with a coupling fork provided between each pair of masses, and with electrodes connected to eliminate gradients.

Abstract: In a multi-stage, multi-residue interpolating analog-to-digital converter (ADC), which is suitable for pipelined implementation, inputs of at least three amplifiers are "leapfrog" switched to adjacent nodes of a first interpolation ladder having discrete voltage levels established thereon. Pairs of the amplifiers drive second interpolation ladders to establish additional discrete voltage levels (in a nominal and an overlap conversion region) at nodes of the second interpolation ladders. A bank of comparators compares a predetermined threshold voltage, e.g., ground, to several of the discrete voltage levels at the nodes of the first interpolation ladder. The switches controlling which inputs of the amplifiers are connected to which nodes of the first interpolation ladder are controlled by a logic circuit which is driven by outputs of the bank of comparators. Alternatively, the bank of comparators compares an input voltage of the ADC to voltage levels established by the first interpolation ladder.

Abstract: A switching bandgap reference circuit with compounded .DELTA.V.sub.BE includes an amplifier having an output, an inverting input and a non-inverting input; a first PN junction connected to the non-inverting input; a second PN junction connected to the inverting input through an input capacitor; a low current source and a high current source; a switching device for applying in the auto zero mode the low current source to a first terminal of the first PN junction and the high current source to a first terminal of the second PN junction for establishing the V.sub.BE, of the first junction at both the inputs of the amplifier and for applying in the valid reference mode the high current source to the first terminal of the first PN junction and the low current source to the first terminal of the second PN junction for establishing the positive .DELTA.V.sub.BE, of the first PN junction to both the inputs of the amplifier and applying the negative .DELTA.V.sub.

Abstract: An apparatus and a method for multiplying two time varying signals to produce a four quadrant, multiplied signal is provided. In one embodiment of the present invention, an apparatus for multiplying a first signal with a second signal includes an analog-to-digital converter that provides a first digital signal representative of the first signal, a first modulator that provides a first modulated signal representative of the second signal, a multiplier that multiplies the first digital signal by the first modulated signal and provides a second digital signal representative of a result of a multiplication of the first signal and the second signal, and a first filter having an input to receive the second digital signal and having an output that provides the multiplied signal.

Abstract: A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.

Abstract: An ESD protection circuit allows a certain level of ESD current to flow through a protected circuit, and actuates a bypass path for greater ESD current levels when the sensed current reaches a threshold level. For a protected circuit having a pair of differential input terminals and a reference voltage terminal, the bypass path is provided between an input terminal which receives an ESD and the reference voltage terminal when the reference voltage is fixed, and between the two input terminals when the reference voltage is floating. The bypass circuit is preferably implemented with a pair of bipolar transistors of a first conductivity that are actuated by an ESD current flow through the protected circuit, and a pair of bipolar transistors of opposite conductivity that are actuated by current flows through the first conductivity transistors.

Abstract: A reference buffer suitable for driving switched-capacitor or resistive load circuits provides a very low output impedance. The reference buffer utilizes an amplifier with a very large and controlled transconductance configured in feedback and compensated by a load capacitance. Cascaded gain stages are used to provide a large, controlled transconductance. In one embodiment, a reference buffer amplifier includes a plurality of voltage gain amplifiers connected in cascade and at least one transconductance amplifier connected to a last-connected of the plurality of voltage gain amplifiers. The amplifier may further include at least one current mirror amplifier connected to the at least one transconductance amplifier. In another embodiment, the reference buffer amplifier includes at least one transconductance amplifier and at least one current mirror amplifier cascade-connected to the at least one transconductance amplifier. The amplifiers can be differential or single-ended.

Abstract: A charge redistribution analog-to-digital converter. This converter includes an offset correcting circuit operatively connected in parallel with a capacitor array and responsive to a sampling input of the analog-to-digital converter, and a gain correcting circuit operatively connected in parallel with a sampling capacitor and responsive to the sampling input of the analog-to-digital converter. In another general aspect, an analog-to-digital converter calibration method for a charge redistribution analog-to-digital converter, that includes adjusting an input offset of an input of the analog-to-digital converter and adjusting a gain offset of the analog-to-digital converter. The steps of adjusting are then repeated until a predetermined level of error is achieved for the analog-to-digital converter.

Abstract: An all npn totem pole TTL output stage is provided with an active regulation circuit that continuously senses the voltage level at the output terminal and feeds it back to control the drive signal that is applied to the base of the bottom output transistor to switch the output state of the load quickly without wasting transient current and then scale back the drive signal during steady state operation to minimize wasted current. When the load is driven into its output low state, the active regulation initially holds the drive signal at a high level so that the load switches quickly. Once the output voltage has fallen low enough, the active regulation reduces the drive signal such that the bottom output transistor is held on the edge of conduction and does not saturate. In this state, the bottom output transistor pulls the output voltage down to approximately ground without conducting any appreciable amount of current.

Abstract: A monolithic capacitance-type microstructure includes a semiconductor substrate, a plurality of posts extending from the surface of the substrate, a bridge suspended from the posts, and an electrically-conductive, substantially stationary element anchored to the substrate. The bridge includes an element that is laterally movable with respect to the surface of the substrate. The substantially stationary element is positioned relative to the laterally movable element such that the laterally movable element and the substantially stationary element form a capacitor. Circuitry may be disposed on the substrate and operationally coupled to the movable element and the substantially stationary element for processing a signal based on a relative positioning of the movable element and the substantially stationary element. A method for fabricating the microstructure and the circuitry is disclosed.

Abstract: A charge pump in a phase locked loop is enabled only when a loop filter needs to be updated, thereby reducing the power consumption of the charge pump. The charge pump is enabled or disabled in response to an enable signal which is generated by a latch. The enable signal is activated by look-ahead signals which are activated in advance of either a pulse from a reference signal or a pulse from a variable signal so as to allow the charge pump to stabilize before providing the charge current to update the loop filter. Logic signals from a programmable divider and reference signal generator are used to generate the look-ahead signals. The charge pump is disabled by a reset signal from a phase-frequency detector after the loop filter is updated. The charge pump includes a current switch for generating source and sink charge currents in response to pump-up and pump-down control signals. A bias cell provides two reference signals to the current switch.

Abstract: A two-stage switched-capacitor residue amplifier having novel circuitry in the first and second stages provides fast and accurate settling while configured with a large closed-loop gain, and also provides low power consumption while powered from a five volt supply. The invention is particularly well suited for use in a multi-stage, pipe-lined analog-to-digital converter (ADC) that converts multiple bits in the first pipeline stage. Complementary PMOS and NMOS differential pairs are used in the first and/or second stage to increase the current slew capability of the amplifier. Current mirror gain and/or positive feedback is used in the second stage to increase transonductance and bandwidth. Cascode transistors are used in the output of the first and/or second stages and active cascode gain enhancement is used in the first stage to increase dc gain and accuracy.

Abstract: A digital-to-analog video encoder method and apparatus having unique equalization are disclosed. The encoder converts digital video signals into one or more analog video formats using one or more digital-to-analog converters. Equalization is provided to compensate for zero order hold effects of the digital-to-analog converters. Equalization is provided to a luminance signal and/or a chroma signal to equalize RGB, composite video, and super VHS video outputs. Multiplexed digital-to-analog converter inputs allow selection of several output formats.

Abstract: A digital signal processor for a PRML system includes: an NMOS pass transistors gain control circuit responsive to a digital data signal for adjusting the gain of the digital data signal; an NMOS pass transistor phase control circuit responsive to the digital data signal for adjusting the phase of the data signal; and an NMOS pass transistor Viterbi maximum likelihood detector circuit for determining the most probable sequence of symbols in the data signal.