Abstract: In one example embodiment, a programmable capacitor array is provided for low distortion and minimizing linearity degradation of an input (Vin) by utilizing control circuitry to switch on and off an array of MOSFET switches. The control circuitry turns on a MOSFET to load a capacitance on Vin and turns off the MOSFET to remove the capacitance from Vin in response to a Din control signal. When the intention is to load Vin with the capacitance, the MOSFET is left on continuously. When the intention is to remove or unload the capacitance from Vin, the MOSFET is primarily turned off, however, the MOSFET is still periodically turned on with appropriate voltage levels in response to a clock signal for periods of time when the loading of the capacitance on Vin is tolerable to the system, thereby ensuring minimal linearity degradation of Vin due to the programmable capacitor array system.

Abstract: In an example embodiment, a circuit is provided that includes a current source with a calibrated trim circuit whose output current varies with transconductance of the current source, and tracks a current mismatch between the current source and another current source under varying bias currents and temperatures. The trim circuit may include at least one calibration digital to analog converter (CAL DAC), which may be driven by a bias circuit generating current proportional to the transconductance of the current source. In an example embodiment, the trim circuit may include at least two CAL DACs, whose output current may vary with bias current only, and with bias current and temperature. A method to calibrate the CAL DACs includes varying calibration settings of the CAL DACs under different bias currents until the output current of the trim circuit substantially accurately tracks the current mismatch under disparate bias currents and temperatures.

Abstract: Apparatus and methods are disclosed, such as those involving a receiver device. One such apparatus includes an equalizer configured to process an input signal transmitted over a channel. The equalizer can include a programmable gain amplifier (PGA) block which includes an input node configured to receive the input signal; an output node; and a programmable gain amplifier (PGA). The PGA amplifies the input signal with an adjustable gain. The PGA block also includes a gain control block having an input electrically coupled to the input node. The gain control block is configured to adjust the gain of the PGA at least partly in response to the input signal from the input node such that the PGA generates an output signal with a substantially constant amplitude envelope to the output node.

Abstract: A target voltage generator for use with a DC to DC converter, the DC to DC converter having a first input for receiving a voltage to be converted, an output for outputting a converted voltage, a first reference voltage input for receiving a first reference voltage and a controller arranged to compare the output voltage of the DC to DC converter with the first reference voltage and to modify the operation of the DC to DC converter so as to reduce a difference between the output voltage and the first reference voltage; the target voltage generator comprising a circuit arranged to compare the output voltage of the DC to DC converter with a second reference voltage and to use a result of the comparison to generate or modify the first reference voltage.

Abstract: A slew rate booster, switchably enabled selector, or other arrangement may be included in a cascode amplifier to keep the current buffer/common gate transistor and the input/common source transistor saturated as the voltage at the source of the current buffer transistor drops during a transient input voltage spike at the gate of the input transistor. In some instances a higher potential may be supplied to a gate of the current buffer transistor during an initial phase of the settling period than during a second phase of the settling period when a lower potential may be applied. Other techniques may be used in different embodiments. Devices and methods are provided.

Abstract: An FFT operation is performed by dividing n time-domain input points into a plurality of groups of m points, performing a plurality of constant-geometry butterfly operations on each of the groups of m points, and finally performing at least one in-place butterfly operation on the group of n points.

Abstract: In an example, there is disclosed a multiple-input analog-to-digital converter configured to receive a plurality of analog inputs and to output one or more digital outputs. In one embodiment, two input analog signals are received. The two analog signals may be mixed in a combiner, which provides them to a pipeline ADC. In another embodiment, the combiner may time multiplex the two analog input signals and provide two separate outputs signals. Advantageously, the multiple-input ADC of the present Specification may be realized with a single ADC pipeline.

Abstract: Various embodiments related to a compact device package are disclosed herein. In some arrangements, a flexible substrate can be coupled to a carrier having walls angled relative to one another. The substrate can be shaped to include two bends. First and second integrated device dies can be mounted on opposite sides of the substrate between the two bends in various arrangements.

Abstract: Cross-talk sensitivity in an xy-axis shell-type gyroscope can be rejected or reduced by operating the gyroscope with a single in-plane flexural or bulk resonance mode and sensing two out-of-plane degenerate or non-degenerate resonance modes resulting from rotations about two axes in the plane of the resonator. Mode matching in an xy-axis shell-type gyroscope can be achieved by configuring the resonator (e.g., size, shape, thickness) to match the in-plane and out-of-plane resonance frequencies for the drive and sense modes of interest.

Abstract: A system and method provide for an adaptive median filter with edge protection and four line buffers to remove the impulse noise for a Bayer pattern image. The system and method separates the Bayer pattern image data into different channels by color and applies the adaptive median filter to remove the impulse noise on each channel. The adaptive median filter has five threshold values that may be modified to achieve different light condition response based on the detected noise level of the image. Thus, proper threshold values with better brightness response to the input pixels may be applied and impulse noise may be suppressed effectively, while preserving image details.

Abstract: Various embodiments provide systems and methods that allow a LIDAR system to sense nearby objects with relatively low-cost elements, and fewer elements than traditional LIDAR systems by sampling an infrared pulse at a high sample rate and storing the samples in the analog domain. The samples may then be digitized at a rate slower than the sample rate.

Abstract: An amplifier includes a fault protection control circuit biased from the signal pin and a fault protection circuit including a first PMOS transistor and a second PMOS transistor. The sources and bodies of the first and second PMOS transistors can be connected to one another, the drain of the first PMOS transistor can be connected to the amplifier's output, and the drain of the second PMOS transistor can be connected to a signal pin. During normal operating conditions, the fault protection control circuit can turn on the first and second PMOS transistors. However, the fault protection control circuit can turn off the first PMOS transistor and turn on the second PMOS transistor when an overvoltage condition is detected, and can turn on the first PMOS transistor and turn off the second PMOS transistor when an undervoltage condition is detected, even when the integrated circuit is unpowered.

Abstract: A voltage monitor comprising a first capacitive potential divider for presenting an attenuated representation of an input voltage to a comparator.

Abstract: An adaptive dead time (ADT) control scheme for use with a switch mode power converter having a full bridge with synchronous rectifiers topology. A controller which implements the control scheme includes an input circuit arranged to receive a signal representative of the converter's output voltage, and an output circuit arranged to operate the converter's switching elements and synchronous rectifiers to produce a desired output voltage. The controller is further arranged such that the converter's “dead time” is adaptively varied in an inverse relationship to the magnitude of the load current. In a preferred embodiment, the signals used to operate the synchronous rectifiers are PWM signals, and the controller adaptively varies the dead time in a linear inverse relationship to the magnitude of the load current by modulating the rising and falling edges of the signals used to operate the synchronous rectifiers.

Abstract: The present disclosure provides for split-path data acquisition chains and associated signal processing methods. An exemplary integrated circuit for providing a split-path data acquisition signal chain includes an input terminal for receiving an analog signal; an output terminal for outputting a digital signal; and at least two frequency circuit paths coupled with the input terminal and the output terminal, wherein the at least two frequency circuit paths are configured to process different frequency components of the analog signal and recombine the processed, different frequency components, thereby providing the digital signal.

Abstract: A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal.

Abstract: A circuit may include a detector, an approximator, a look-up table, a scaler, and an integrator. The detector may generate a first difference signal and a second different signal based on an input and an output. The approximator may generate, using a one's complement operation, an index based on approximated modulus values of the first difference signal and the second difference signal. The look-up table may select one of a plurality of scaling factors based upon the index. The scaler may adjust the first difference signal and the second difference signal based on the selected scaling factor. The integrator may generate the output based on the adjusted first difference signal and the adjusted second difference signal.

Abstract: A device or system that incorporates teachings of the present disclosure may include, for example, a resonant structure having a plate, a mass and a set of electrodes. The plate can have an extensional mode at a frequency when excited. The set of electrodes can be used to measure an acceleration of the mass when the acceleration of the mass changes the frequency of the plate. Other embodiments are disclosed.

Abstract: A method for balancing an electrical parameter (e.g, a current or a voltage) between phases in a multi-phase interleaved circuit includes sensing the electrical parameter, demultiplexing the electrical parameter in accordance with a phase-select signal, sampling the demultiplexed components into a plurality of digital signals, generating an error signal based on a difference between the digital signals, and modulating the phase-select signal, as applied to the phases, in accordance with the error signal.

Abstract: A symmetric object in an image is identified by (a) converting an edge map of the acquired image into a binary image map including binary pixel values; (b) dividing the binary image map within a scanning window into multiple bins; (c) summing binary pixel values in each bin; and (d) identifying the symmetric object based at least in part on the summed binary pixel values in the bins.