Abstract: Signal IO protection devices referenced to a single supply are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power supply network, such as a power low supply network or a power high supply network. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. In other implementations, a protection device includes first and second SCRs for providing protection between the signal node and the power low supply network or between the signal node and the power high supply network, and the SCR structures are integrated in a common circuit layout. The protection devices are suitable for single cell data conversion interface protection to a single supply in sub 3V operation.

Abstract: Embodiments of the present invention may provide an analog-to-digital converter (ADC) system. The ADC system may include an analog circuit to receive an input signal and a reference voltage, and to convert the input signal into a raw digital output. The analog circuit may include at least one sampling element to sample the input signal during a sampling phase and reused to connect to the reference voltage during a conversion phase, and an ADC output to output the raw digital output. The ADC system may also include a digital processor to receive the raw digital output and for each clock cycle, to digitally correct reference voltage errors in the analog-to-digital conversion.

Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit generates a detection signal in response to a transient electrical stress. First and second driver circuits of an integrated circuit, each driver having one or more bipolar junction transistors, activate based on the detection signal and generate activation signals. The one or more bipolar junction transistors of the first and second driver circuits are configured to conduct current substantially laterally across respective base regions. A discharge circuit, having an upper discharge element and a lower discharge element, receives the activation signals and activates to attenuate the transient electrical event.

Abstract: A clock shifter circuit may receive a input clock in a first voltage domain and may generate a level-shifted output clock in a second voltage domain. The circuit may include a cross-coupled pair of transistor switches and a pair of capacitors. Each switch may have a drain coupled to one of the capacitors, a source coupled to a circuit supply voltage, and a gate coupled to the other capacitor. One capacitor may receive a true input clock version, while the other may receive a complement version. Each capacitor, in an alternating manner, may activate an opposing transistor switch to charge its capacitor during an active phase of its respective input clock. The circuit may generate the output clock from an output node connected between one of the transistor switches and its capacitor. The output clock may drive a load directly coupled to the output node.

Abstract: A system architecture allows for the transmission of multiple HDCP encrypted audio/video streams over a single unified cable to multiple receivers using a daisy chain topology. Each individual audio/video stream is first encrypted and then combined into a uniform stream, and the uniform stream is transmitted to each of the receivers. Each receiver contains a decryption engine that operates independently of the engines in the other receivers, therefore allowing each receiver to select to a unique channel and decrypt and display one of the audio/video streams.

Abstract: A circuit may include one or more transistors connected directly to an output, and an inductance network. The inductance network may connect to a source node of at least one of the transistors, to compensate capacitance of the output. Thus, the response time of the circuit may decrease, and a non-dominant frequency response pole frequency of the circuit may increase.

Abstract: A circuit may include one or more transistors connected directly to an output, and a biasing network connected to at least one of a substrate, a well, and a back-gate of at least one of the transistors. The biasing network may biase the at least one of the substrate, the well, and the back-gate to a virtual floating bias, such that the virtual floating bias shifts in voltage level based upon an AC input signal of the circuit, to reduce the parasitic capacitance of the output node of the circuit.

Abstract: Low power low noise input bias current compensation for an amplifier input stage is provided by recycling the tail current of the differential pair transistors. A local amplifier regulates the tail current and buffers the base current of the tail current transistor, which is mirrored back to the input transistors to provide input bias current compensation.

Abstract: Circuits and methods are introduced to allow for timing relationship between a clock signal and a synchronization signal to be observed. The observations may include observing the timing relationship between a capture edge of the clock signal and a transition of the synchronization signal. Based on the observations the timing of the synchronization signal transition may be adjusted. Observing the timing relationship may include providing a delayed synchronization signal and a delayed clock signal. The delayed synchronization signal may provide what happens before the capture edge of the clock signal. The delayed clock signal may provide what happens after the capture edge of the clock signal.

Abstract: A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.

Abstract: As provided herein, in some embodiments, monolithic oscillators with low phase noise, large swing voltages, wide tuning, and high frequency characteristics are obtained by a monolithic integrated circuit having an oscillator core configured to generate a first output signal, and one or more tuning units operatively coupled to the oscillator core. In some embodiments, the oscillator core is a push-push oscillator core having a bipolar junction transistor, and each of the tuning units uses a FET transistor to present a selectable capacitance. In some embodiments, the tuning units have high-voltage and high-frequency capabilities. In some embodiments, the tuning units use MEMS switches to selectively connect capacitances to the oscillator core. In some embodiments, the oscillator core generates a second signal that has twice the frequency of the first frequency.

Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).

Abstract: Apparatus and methods are disclosed related to an oscillator that includes a sustaining amplifier. One such apparatus includes a resonant circuit configured to operate at a resonant frequency, a sustaining amplifier, and a passive impedance network. The resonant circuit can have a first terminal and a second terminal. The sustaining amplifier can include at least a first switch configured to drive the first terminal of the resonant circuit in response to an input at a first control terminal of the first switch. The passive impedance network can be configured to pass a bias to the first control terminal, such as a gate of a field effect transistor, of the first switch. The passive impedance network can be electrically coupled to the second terminal of the resonant circuit and can include at least one inductor.

Abstract: A buck converter comprising a controller arranged to monitor an output voltage of the converter, the controller comprising: a comparator arranged to compare an output voltage at an output of the buck converter with a reference voltage, and a modification circuit within the comparator or connected to a modification signal input of the comparator and arranged to produce a correction signal to modify the operation of the comparator; and an output.

Abstract: In one example implementation, the present disclosure provides a direct current (DC) restoration circuit for restoring the DC component of a synchronization signal provided over an alternating current (AC) coupled link from a transmitting circuit to a receiving circuit. During a period of inactivity in the synchronization signal, the synchronization signal may experience a drift towards the common mode, and may affect the ability for the synchronization signal to properly trigger the receiving circuit. The DC restoration circuit is configured to hold the synchronization signal steady during the period of inactivity, and allow the AC component of the synchronization signal pass through to the receiving circuit during the period of activity to alleviate the problem of baseline drift in the synchronization signal.

Abstract: A system and method to detect the fundamental frequency of an electric input signal using a feedback control loop including a phase error detector, a loop controller, and a digitally controlled oscillator. The frequency detector may detect the fundamental frequency of an electric input signal and produce an output signal representing the fundamental frequency of the electric input signal. The frequency detector may further include a filter that may be coupled to the frequency detector output signal in order to remove spurious tones or noise from the output signal.

Abstract: Various embodiments related to a compact device package are disclosed herein. In some arrangements, a flexible substrate can be coupled to a carrier having walls angled relative to one another. The substrate can be shaped to include two bends. First and second integrated device dies can be mounted on opposite sides of the substrate between the two bends in various arrangements.

Abstract: One embodiment relates to a method of compensating for crystal frequency variation over temperature. An example method includes obtaining an indication of temperature, computing a temperature compensation value based on the indication of temperature and a piecewise linear temperature compensation approximation, and compensating for a temperature offset in a crystal reference signal by adjusting a division ratio of a fractional divider in a phase-locked loop. The piecewise linear temperature compensation approximation can represent an approximation of frequency error in a crystal reference signal originating from a crystal over temperature. The piecewise linear temperature compensation approximation can be, for example, a linear approximation, a quadratic approximation, or a cubic approximation.

Abstract: Embodiments of the present invention may provide a signal processor with a wide gain range. The signal processor may comprise at least a discrete step gain stage and a continuous variable gain amplifier (VGA) stage. The discrete step gain stage may comprise a programmable gain amplifier (PGA) (e.g., low noise amplifiers 1 and 2 (LNA1 and LNA2)). The VGA stage may provide a continuous range to compensate the LNAs gain steps. In one embodiment, the AGC controller enables an inherent hysteresis with the AGC step change if required.

Abstract: Apparatus and methods are also disclosed related to an oscillator that includes a switching network configured to tune a resonant frequency of a resonant circuit. One such apparatus includes a switching network having a circuit element, such as a capacitor, that can be selectively coupled to the resonant circuit by a switch, such as a field effect transistor. For instance, the switch can electrically couple to circuit element to the resonant circuit when on and not electrically couple the circuit element to the resonant circuit when off. An active circuit can assert a high impedance on an intermediate node between the switch and the circuit element when the switch is off.