Abstract: A mixer includes an input stage to convert an RF input signal to an output signal, and a mixer core to mix the output signal from the input stage with a local oscillator signal. The input stage may include an input cell having a first differential pair of cross-connected transistors, and a linearizer coupled to the input cell. The linearizer may include a second differential pair of transistors having first and second inputs coupled to the input terminals and first and second outputs coupled to the output terminals.

Abstract: A method of detecting activity with a MEMS accelerometer stores a value of acceleration, then measures acceleration at a later time, calculates a change in acceleration using the measured acceleration and the stored acceleration, and compares the change in acceleration to an activity threshold to detect activity. A method of detecting inactivity uses a similar technique along with a timer. The method of detecting inactivity with a MEMS accelerometer stores an acceleration value, then measures acceleration at a later time, calculates a change in acceleration using the measured acceleration and the stored acceleration, and compares the change in acceleration to an inactivity threshold. If the change in acceleration is less than the inactivity threshold and, if a predetermined period of time has elapsed, then inactivity is detected.

Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply.

Abstract: Apparatus and methods for monolithic data conversion interface protection are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power high supply node, a second SCR and a second diode for providing protection between the signal node and a power low supply node, and a third SCR and a third diode for providing protection between the power high supply node and the power low supply node. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. Configuring the protection device in this manner enables in-suit input/output interface protection using a single cell. The protection device is suitable for monolithic data conversion interface protection in sub 3V operation.

Abstract: A MEMS apparatus has a substrate, a cap forming first and second chambers with the base, and movable microstructure within the first and second chambers. To control pressures, the MEMS apparatus also has a first outgas structure within the first chamber. The first outgas structure produces a first pressure within the first chamber, which is isolated from the second chamber, which, like the first chamber, has a second pressure. The first pressure is different from that in the second pressure (e.g., a higher pressure or lower pressure).

Abstract: In one example embodiment, a programmable filter is provided, including a plurality of variable-inductance networks and a plurality of variable-capacitance networks. The programmable filter may be implemented in a classical filter topology, with variable-capacitance networks replacing discrete capacitors and variable-inductance networks replacing discrete inductors. An example variable-inductance network comprises a primary inductor with an intermediate tap, and secondary inductor connected at the intermediate tap, with switches for selecting an inductance.

Abstract: Systems and methods for amplitude compressing a digital signal. An input signal is divided into frames having a first and second sets of samples. The samples in the second set are also in a subsequent frame. Peak values are determined for the first and second sets. One or more slopes are calculated based on the peak values. The slopes are used to define a scale factor which is applied to the first set to produce the output signal. For example, if the first peak value exceeds an amplitude threshold, first and last samples in the first set to exceed the amplitude threshold are found. Slopes are calculated for each of three regions of the first set demarcated by the first and last samples. In each region a slope is selected. These slopes along with an initial scale factor are used to calculate the scale factor.

Abstract: A multiplexing circuit comprising an converter for converting an input voltage signal to an input current signal. A plurality of first current mirrors for mirroring the input current signal. A switching unit selectively switches each first current mirror to a corresponding output.

Abstract: The invention may provide a receiver including a front-end block to provide a front-end gain on a radio-frequency input signal. The front-end block may include a mixer to convert the radio-frequency input signal to a baseband signal. The receiver also may include a wide-band peak detector coupled to the front-end block and a baseband block to provide a baseband gain on the baseband signal. An analog-to-digital converter may convert the baseband signal to a digital signal. The receiver may further include narrow-band peak detector coupled to an output of the analog-to-digital converter. An automatic gain control circuit may independently control the front-end gain and the baseband gain based on outputs from the wide-band peak detector and narrowband peak detector.

Abstract: A radio frequency diode detector has a set of diodes having a differential voltage output, and a current source electrically coupled to the ring of diodes, the current source coupled to provide a forward bias current. This is followed by nonlinear signal processing to create an overall linear detector suitable for use in microwave power measurement.

Abstract: Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.

Abstract: A switching regulator and control method for the same. The switching regulator employs a hybrid mode. A ramp voltage signal is added to the current sense signal to make the ramp voltage signal overtake the current information when the duty cycle becomes low.

Abstract: A fully on-chip clock generator on an integrated circuit (“IC”) includes a frequency detector for receiving a reference current and providing a first voltage; an error integrator for receiving the first voltage from the frequency detector, comparing it with a reference voltage, and providing a control voltage; a voltage controlled oscillator (“VCO”) for receiving the control voltage from the error integrator, and providing an output clock; and a logic controller on the IC, coupled between the VCO and the frequency detector, and generating logic control signals for controlling the frequency detector. The fully on-chip clock generator requires no external crystal, but its power consumption is significantly lower than a relaxation oscillator that generates the same clock frequency.

Abstract: In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.

Abstract: Systems and methods to determine locations for dual touch operations performed on a four-wire resistive touch screen. The systems and methods may include measuring signals from pairs of electrodes on each of a first and second resistive sheet of the resistive touch screen in two phases of operation. The systems and methods may further include determining touch screen segment resistances from the signal measurements. The systems and methods may determine locations corresponding to the dual touch operations from the resistances. The systems and methods may also determine locations from the signal measurements.

Abstract: Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices.

Abstract: A receiver architecture for processing spread spectrum signals. The receiver has an RF front end to receive and down convert a broadcast signal to an intermediate frequency carrier. The IF signal is digitized and provided to a processor (which may be a software-driven DSP, an ASIC or other embodiment) for processing. A given IF carrier is removed and the signal is low pass filtered. The signal is provided to a number of channels, each, for example, correspond to a unique transmitter. On each channel the sample rate is reduced to a predetermined fixed rate with timing mismatch compensated. The Doppler frequency shift, as estimated for the channel, is removed succeedingly. A locally generated copy of the spreading code used by the transmitter is applied to the carrier and Doppler removed signal at the predetermined fixed sample rate. The de-spread signal is used to provide estimates of the Doppler shift and for subsequent sample selection.

Abstract: A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal.

Abstract: An integrated, fully-differential current-feedback transimpedance operational amplifier circuit is disclosed. The circuit can be configured as a class-AB, low-impedance input stage, followed by an inverter-based, rail-to-rail output stage. For enhancing the open-loop transimpedance gain of the amplifier without consuming additional DC power, the same bias current is used both in the input stage and in a gain-enhancement stage serving as its load. The gain-enhancement stage can be either DC- or AC-coupled to the input of the amplifier. In the case of DC coupling, an output common-mode feedback loop can be used to provide the proper operating voltages in the amplifier.

Abstract: An integrated device package includes a housing having a first opening and a second opening in fluid communication with an interior volume of the housing. A package substrate(s) has a first port and a second port. A first device die is mounted to the substrate(s) over the first port. A second device die is mounted to the substrate(s) over the second port. The substrate(s) is coupled to the housing to cover the first and second openings such that the first device die is disposed within the interior volume through the first opening and the second device die is disposed within the interior volume through the second opening.