Abstract: In an embodiment of the invention, a differential input signal is coupled to a plurality of transconductance blocks. In some embodiments, each of the transconductance blocks divide an input transconductance among a plurality of signal paths to a plurality of outputs in each transconductance block. In an embodiment, the input transconductance may be divided based a ratio of transistor areas in the plurality of signal paths, though other embodiments may divide the transconductance differently. In some embodiments, transconductance block outputs of a plurality of transconductance blocks may be cross-coupled to provide a gain path for a differential signal than is greater than that of a common mode signal.

Abstract: A first output count is compared with first and second stored count values for generating an output event at a first node if the first Output count corresponds to the first or second stored count values.

Abstract: A micromachined microphone is formed from a silicon or silicon-on-insulator (SOI) wafer. A fixed sensing electrode for the microphone is formed from a top silicon layer of the wafer. Various polysilicon microphone structures are formed above a front side of the top silicon layer by depositing at least one oxide layer, forming the structures, and then removing a portion of the oxide underlying the structures from a back side of the top silicon layer through trenches formed through the top silicon layer. The trenches allow sound waves to reach the diaphragm from the back side of the top silicon layer. In an SOI wafer, a cavity is formed through a bottom silicon layer and an intermediate oxide layer to expose the trenches for both removing the oxide and allowing the sound waves to reach the diaphragm. An inertial sensor may be formed on the same wafer, with various inertial sensor structures formed at substantially the same time and using substantially the same processes as corresponding microphone structures.

Abstract: Embodiments provide for a method for eliminating pathological sequences in a serial bit stream. Parallel data words having a first bit length are received. The received data words may be analyzed for a pathological sequence. If a pathological sequence is present in a data word, the data word containing the pathological sequence may be segmented into data segments having bit lengths less than a pathological sequence. The data word may be reformatted by generating reformatted data words having a second bit length. The reformatted data words may contain at least one of the data segments and the second bit length is greater than the first bit length. The reformatting may be performed by adding framing bits to the segments to form the reformatted data words. The reformatted data words are transmitted in place of the data word containing the pathological sequence.

Abstract: A method and system of sample recovery is disclosed. In one embodiment, a method includes selecting initially in an arbitrary manner, a current symbol from a sequence of input samples, comparing a symbol timing estimate associated with the current symbol to a predetermined threshold, selecting a future symbol strobe that is ahead at an interval equivalent to a predetermined interval based on the comparison of the symbol timing estimate to the predetermined threshold, selecting a future symbol from the sequence of samples corresponding to the future symbol strobe, assigning the future symbol to the current symbol, which is the recovered symbol, rearranging the recovered symbols to form Pulse Code Modulated (PCM) samples of a bandlimited signal at a sample rate which is derived from the recovered symbol rate, and resampling at the sample rate of the receptor block which receives the recovered PCM samples.

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract: A scalable highest available voltage selector circuit determines the highest of n input voltages and connects the highest voltage to an output. The circuit has at least n circuit branches, each of which comprises n?1 “comparator” FETs connected between an input voltage and an output node, and a diode-connected FET connected between the output node and a current source. The junction of the diode-connected transistor and current source provides a control signal used by the other branches. Each of a branch's comparator FETs have their gates connected to a respective one of the other branches' control signals, such that they are driven on regeneratively when the applied input voltage is the highest of the n input voltages. Each branch also includes n?1 “shorting” FETs connected across the diode-connected transistor, arranged to be driven off when the applied input voltage is the highest, but which are otherwise driven on.

Abstract: A battery monitoring system is provided to monitor a battery stack having multiple cells connected in series. The monitoring system includes monitor modules to monitor respective subsets of the cells of the battery stack, each monitor module, in response to one or more control signals, measuring cell voltages of the respective subset of cells and providing at least one readout signal that represents the sampled cell voltages, the monitor modules being electrically connected in a stack such that each monitor module is referenced to the voltage of the respective subset of cells, and the control signals and the readout signal are connected through the monitor modules of the stack, and a system control unit to provide the control signals to the monitor modules and to receive the readout signals from the monitor modules.

Abstract: A selectable gain amplifier includes two or more selectable gain stages, each gain stage having a first input coupled to receive an input signal, a second input, and an output. The amplifier further includes and two or more feedback paths coupled between the outputs and the second inputs of the selectable gain stages.

Abstract: A microphone system has a base coupled with first and second microphone apparatuses. The first microphone apparatus is capable of producing a first output signal having a noise component, while the second microphone apparatus is capable of producing a second output signal. The system also has combining logic operatively coupled with the first microphone apparatus and the second microphone apparatus. The combining logic uses the second output signal to remove at least a portion of the noise component from the first output signal.

Abstract: A MEMS microphone has a backplate and a movable diaphragm that together form a variable capacitance. The backplate has a backplate surface and, in a corresponding manner, the diaphragm has a diaphragm surface that faces the backplate surface. At least one of the backplate surface and the diaphragm surface has at least a portion with a Hurst exponent that is less than or equal to about 0.5.

Abstract: A single integrator sensorless current mode control scheme for a switching power converter requires an amplifier circuit which produces an first current that varies with the difference Verror between a reference voltage and a voltage that varies proportionally with Vout, a circuit which produces a second current that varies with the voltage VL across the output inductor, a single integrating element connected to receive the first and second currents such that it integrates both Verror and VL, and a comparator which receives the integrated output at its first input and a substantially fixed voltage at its second input and produces an output that toggles when the voltage at its first input increases above and falls below the substantially fixed voltage. The comparator output is used to control the operation of the power converter's switching circuit and thereby regulate the output voltage.

Abstract: A switching circuit for switchably connecting an input node and an output node. The switching circuit comprises a switch operable to switchably connect the input node to the output node in response to a switching signal. A sensor is provided for sensing the voltage between the input and output nodes and providing a sense signal in response thereto. A driver coupled to the sensor adjusts the switching signal in response to the sense signal.

Abstract: An input bias current cancellation circuit includes reference transistors placed in series and a current summation network. The current summation network can be configured to sum the base currents of the reference transistors to produce a summed current. A current mirror can be provided to attenuate the summed current to produce input bias cancellation currents. The input bias cancellation currents can be provided to the base inputs of an input bipolar differential pair, thereby reducing input current noise.

Abstract: As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. A bias circuit arrangement with an output substantially decoupled from changes in the voltage supply level may provide a more stable operating point in an active circuit.

Abstract: An amplifier has an input section with one or more input cells and an output section with one or more output cells. Either the input section or the output section includes at least two cells that may be selected to provide discrete gain settings. A loop amplifier is configured in a feedback arrangement with the input section. The input and output sections may have multiple selectable cells to provide coarse and fine gain steps. The gain of the loop amplifier may be coordinated with the gain of the input section to provide constant bandwidth operation.

Abstract: A MEMS switch with a platinum-series contact is capped through a process that also passivates the contact by controlling, over time, the amount of oxygen in the environment, pressures and temperatures. Some embodiments passivate a contact in an oxygenated atmosphere at a first temperature and pressure, before hermetically sealing the cap at a higher temperature and pressure. Some embodiments hermetically seal the cap at a temperature below which passivating dioxides will form, thus trapping oxygen within the volume defined by the cap, and later passivate the contact with the trapped oxygen at a higher temperature.

Abstract: An integrator is described that may include a level-shifting capacitor, a feedback capacitor, a pre-amplifier stage and a multi-path amplifier module. The integrator may have inputs for connected an input signal source to the level-shifting capacitor. The level-shifting capacitor is connected to an input of a pre-amplifier stage of an integration signal path and to the input. The level-shifting capacitor may level shift the voltage at the input of the circuit to a lower voltage at the input of the pre-amplifier stage. Thereby, the supply voltage to the pre-amplifier stage may be reduced as well as have limited power consumption, limited temperature rise, and reduced noise that may be attributed to any thermal effects.

Abstract: The problems of large oscillator signal frequency change per bit, small runtime tuning bandwidth, and large wiring layout (and therefore large integrated circuit (IC) layout) in digitally-controlled oscillators are addressed by using an array of addressable tuning units, storing a data bit with respect to each tuning unit, and based on the data bit and an address bit, adjusting the output of each tuning unit.

Abstract: In one aspect, a software application for facilitating design of a register specification is provided. The application comprises an interface adapted to receive input from a user indicating information about at least one register in the register specification, the interface generating register information based on the received input, a translator coupled to the interface to receive the register information and adapted to convert the register information to an internal representation, and at least one filter adapted to transform the internal representation into at least one respective output format.