Abstract: A circuit may include one or more transistors connected directly to an output, and an inductance network. The inductance network may connect to a source node of at least one of the transistors, to compensate capacitance of the output. Thus, the response time of the circuit may decrease, and a non-dominant frequency response pole frequency of the circuit may increase.

Abstract: Time-of-flight technology may be combined with optical detection technology identifying an angle of a light pulse emitted from a transmitter and reflected off an object based on a proportion of the reflected light pulse detected at each of at least two light sensors. The optical detection technology may include a light detector with two or more light sensors arranged at different orientations with respect to an aperture in the detector so that each sensor is able to detect a different subset of the light passing through the aperture. The effective angle of the light passing through aperture may then be calculated from the proportion of light detected at the each of the sensors. The effective angle information may be combined with a calculated time-of-flight of the light pulse to accurately identify a position of the object relative to the detector in two or three dimensions.

Abstract: An apparatus for transceiver signal isolation and voltage clamp from transient electrical events includes a bi-directional protection device comprising a bipolar PNPNP device assembly, a first parasitic PNPN device assembly, and a second parasitic PNPN device assembly. The bipolar PNPNP device assembly includes an NPN bi-directional bipolar transistor, a first PNP bipolar transistor, and a second PNP bipolar transistor, and is configured to receive a transient voltage signal through first and second pads. The first and second pads are electrically connected to the PNPNP device assembly through emitters of the first and second PNP bipolar transistors. The bipolar PNPNP device assembly is electrically connected to a first parasitic PNPN device assembly comprising a parasitic PNP bipolar transistor and a first parasitic NPN bipolar transistor.

Abstract: A method and apparatus for protecting access to sensitive information stored in vulnerable storage areas (e.g., public memory, registers, cache) of a microprocessor. A microprocessor having a reset port to receive external reset commands may have a reset diversion circuit that may be selectively enabled. The microprocessor may operate in an open mode or a secure mode, indicating the absence or the potential presence, respectively, of sensitive information in the vulnerable storage areas. In open mode, the reset diversion circuit may be disabled such that external reset requests triggers a hardware reset. In secure mode, sensitive information may be recorded on vulnerable storage areas. The reset diversion circuit may be enabled to divert external reset requests to an interrupt which may trigger execution of a software code. The software code, when executed, may perform a secured system clean-up routine to erase the vulnerable storage areas prior to reset.

Abstract: Contours of objects appearing in a digital image are extracted in a plurality of one-directional passes across the digital image. Each pass loads rows or columns of the image into a local memory, in the order they appear in the image, and analyzes them for the presence of portions of the full contour. The portions are then combined to create the full contour.

Abstract: In one aspect, a current source is provided to limit noise and offset. In one embodiment, a source transistor is provided, with current sourced at the drain. A feedback network runs from the source node to the gate. The feedback network produces voltage gain by a transconductance, such as a transistor. Appropriate capacitors are also provided, and two pairs of switches are disposed to provide offset cancellation by toggling between gain and clamp modes in the switched capacitor architecture.

Abstract: A circuit may include one or more transistors connected directly to an output, and a biasing network connected to at least one of a substrate, a well, and a back-gate of at least one of the transistors. The biasing network may bias the at least one of the substrate, the well, and the back-gate to a virtual floating bias, such that the virtual floating bias shifts in voltage level based upon an AC input signal of the circuit, to reduce the parasitic capacitance of the output node of the circuit.

Abstract: Apparatus and methods for amplifier input protection are provided. In certain implementations, an amplifier input protection circuit includes a first JFET electrically connected between a first input and a first output, and a second JFET electrically connected between a second input and a second output. Additionally, a first clamp is electrically connected to the first output, and a second clamp is electrically connected to the second output. A first current mirror mirrors a current through the first clamp, and provides the mirrored current to a third JFET electrically connected between the first JFET's source and gate. Additionally, a second current mirror that mirrors a current through the second clamp, and provides the mirrored current to a fourth JFET that is electrically connected between a source and gate of the second JFET. Configuring the protection circuit in this manner can provide the benefits of both low noise and low fault current.

Abstract: A security-aware master is provided, such that a master can determine its security state before attempting access to secure resources or before requesting secure access level. An exemplary system include a system interconnect; one or more masters coupled with the system interconnect; and a master security check register coupled with the system interconnect. The master security check register is configured to receive a request from a master via the system interconnect to access the master security check register, wherein the request includes a master operating state signal that indicates a security state of the master requesting access, and return a data value to the master based on the master operating state signal, wherein the data value indicates a current security state of the master requesting access.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: A wireless charging network system is disclosed that includes wirelessly charged sensor nodes. The wireless network system can include a gateway node configured to aggregate data from sensor nodes within a coverage area of the gateway node. The gateway node is further configured to wirelessly transmit power to the sensor nodes using a beamformed signal, wherein the gateway node adjusts the beamformed signal to maximize wireless power transfer to sensor nodes within each sector of the coverage area. Location information can be used to adjust the beamformed signal. For example, in various embodiments, the gateway node includes a beamformer sector profile table that defines channel adaptive beam profiles for the beamformed signal for each sector of the coverage area. The gateway node can use location information to define the beam profiles.

Abstract: A wireless charging platform for a wireless sensor network is disclosed, which includes a radio frequency energy distributor and data aggregator (REDDA) system configured to aggregate data from sensor nodes and wirelessly transmit power to the sensor nodes using a beamformed RF signal. The REDDA system can set a radiation pattern for the beamformed RF signal that maximizes RF energy transfer to the sensor nodes based on an environment associated with the sensor nodes. In various embodiments, the REDDA system can include an Internet of Things (IoT) interface connected to an IoT network, and the REDDA system can use information gleaned from the IoT network to set the radiation pattern.

Abstract: In certain applications, differential amplifiers with infinite common mode rejection ratios are desirable. However, resistance mismatches due to imperfections in the manufacturing create finite common mode rejection ratio in differential amplifiers degrading their performance. Disclosed are apparatus and method for improving the common mode rejection ratio of practical differential amplifiers.

Abstract: A LED drive system for controlling an off-chip power supply enables the power supply function to be located ‘off-chip’—i.e., on an IC which is separate from the IC containing the other LED drive system components. The off-chip supply provides a common line voltage for LED strings connected in series with respective current sink circuits at respective junctions, in response to a signal applied to a control input. The system includes a ‘minimum’ circuit which outputs the least of the voltages at the junctions, and an I/O pin which receives a signal that varies with the output of the minimum circuit. When the external supply's control input is coupled to the system's I/O pin, the present system controls the output of the external power supply as needed to provide a desired common line voltage.

Abstract: System and method to detect battery cell malfunctions through redundant offset battery cell monitoring. Redundant battery monitoring may be implemented in a battery monitoring system to process battery cell voltages at offset times. A processor may compare offset voltage samples for a particular battery cell. If the samples vary outside a predetermined range, the processor may indicate a battery cell malfunction.

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract: A method of detecting enclosure leakage of an electrodynamic loudspeaker mounted in an enclosure or box may include applying an audio signal to a voice coil of the electrodynamic loudspeaker through an output amplifier and detecting a voice coil current flowing into the voice coil. A voltage across the voice coil may be detected and an impedance or admittance of the loudspeaker across a predetermined audio frequency range may be detected based on the detected voice coil current and voice coil voltage. A fundamental resonance frequency of the loudspeaker may be determined based on the detected impedance or admittance and compared with a nominal fundamental resonance frequency of the loudspeaker representing a sealed state of the enclosure. Acoustic leakage of the enclosure may be detected based on a deviation between the determined the fundamental resonance frequency and the nominal fundamental resonance frequency of the electrodynamic loudspeaker.

Abstract: An integrated device package includes a housing having a first opening and a second opening in fluid communication with an interior volume of the housing. A package substrate(s) has a first port and a second port. A first device die is mounted to the substrate(s) over the first port. A second device die is mounted to the substrate(s) over the second port. The substrate(s) is coupled to the housing to cover the first and second openings such that the first device die is disposed within the interior volume through the first opening and the second device die is disposed within the interior volume through the second opening.

Abstract: A DC-to-DC converter includes an error integrator that further includes a first amplifier and a second amplifier that each includes a first input for receiving a reference voltage and a second input for receiving a feedback voltage, a capacitor to an output of the second amplifier, and a resistor including a first end being coupled to an output of the first amplifier and a second end being coupled to the capacitor.

Abstract: Methods and devices for calculating the position of a movable device are disclosed. The device may include multiple optical detectors (ODs) and the movable device may include light sources. Optics may be above the ODs. A controller may calculate the position of the light source based on data from the ODs and properties of the optics. The device may be a game console, and the light source may be a game controller. The roles of the OD and light sources may be interchanged. The rotation of the movable device may be determined using multiple light sources and/or multiple ODs on the movable device. The movable device may calculate its position and transmit it to a console. The light sources may be modulated by time or frequency to distinguish between the light sources. There may be two or more movable devices. There may be two or more consoles.