Abstract: Practical electronics such as amplifiers or voltage references can have circuit imbalances due to manufacturing imperfections. For example, amplifiers can have an undesirable offset voltage. The offset voltage might also drift with temperature making the design of these devices difficult. Disclosed are techniques which decrease the amount of offset voltage which provide predictability of device parameters over a range of temperatures.

Abstract: Apparatus and methods for chopper amplifiers are provided herein. In certain configurations, a chopper amplifier includes at least one differential transistor bank including a selection circuit and a plurality of transistors. The selection circuit can select a first portion of the transistors for operation in a first transistor group and a second portion of the transistors for operation in a second transistor group. During calibration, the chopper amplifier's input offset can be observed for different transistor configurations of the differential transistor banks. Although the transistors of a particular bank can be designed to have about the same drive-strength and/or geometry, the chopper amplifier can have a different input offset in different transistor configurations due to manufacturing mismatch between transistors, such as process variation.

Abstract: In an example, there is disclosed a system and method for detecting and correcting error in a quadrature receiver (QR). The QR may include a receiver channel operable to divide a received RF signal into I and Q channels. The receiver channel may include error sources, such as (in sequence) pre-demodulation (PD) error, LO mixer error, and baseband (BB) error. Test tones may be driven on the receiver channel at a plurality of test frequencies, and a quadrature error corrector may be provided to detect error from each source. Upon receiving an RF signal, the quadrature error corrector may apply correction coefficients to correct each source of error in reverse sequence (BB, LO, PD).

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Abstract: A transconductance gain stage including a pair of gain transistors, each gain transistor having a base and an emitter, the emitter of each gain transistor electrically coupled to a degenerating resistor, and the emitter of each gain transistor connected to a gain resistor.

Abstract: Various methods and systems are provided to control a probe moving towards fluid held in a container. The probe is moved towards the fluid to take a sample of the fluid in the container. To take a sample, probe is actuated to hit the fluid surface and to pass the fluid surface by a predetermined distance. Capacitive sensing which incorporates the probe itself is used to support an approach engine for controlling the motion of the probe. The approach engine determines the speed of the probe based on capacitance measurements, and in some cases based on position information of the probe. The approach engine ensures the probe hits the surface of the fluid in the container in order to take a sample while ensuring the probe does not hit the bottom of the container.

Abstract: In an example, there is disclosed a system and method for detecting and correcting error in a quadrature receiver (QR). The QR may include a receiver channel operable to divide a received RF signal into I and Q channels. The receiver channel may include error sources, such as (in sequence) pre-demodulation (PD) error, LO mixer error, and baseband (BB) error. Test tones may be driven on the receiver channel at a plurality of test frequencies, and a quadrature error corrector may be provided to detect error from each source. Upon receiving an RF signal, the quadrature error corrector may apply correction coefficients to correct each source of error in reverse sequence (BB, LO, PD).

Abstract: A method for aligning an opto-electronic component in an IC die with an optical port is disclosed. This is achieved, in various embodiments, by forming alignment features in the IC die that can mate with complementary alignment features of the optical port. The formation of alignment features can be performed at the wafer level during fabrication of the IC die. An optical signal carrier may be optically coupled to the optical port such that the signal carrier may communicate optically with the opto-electronic component.

Abstract: An apparatus comprises a power converter circuit and a control circuit. The power converter circuit includes a primary circuit side and a secondary circuit side. The primary circuit side includes a plurality of primary switches, and the secondary circuit side includes a plurality of synchronous rectifiers and an inductor. The control circuit is configured to operate the synchronous rectifiers synchronously with the primary switches when inductor current at the inductor is greater than or equal to a reference inductor current, and operate the synchronous rectifiers in a bidirectional mode when the inductor current is less than the reference inductor current, wherein energy is delivered from the primary side to the secondary side and from the secondary side to the primary side during the bidirectional mode.

Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.

Abstract: A slave-interface unit for use with a system-on-a-chip bus (such as an AXI bus) executes received transactions out-of-order while accounting for groups of in-order transactions.

Abstract: A tunable impedance circuit can include a fixed impedance and one or more impedance selection circuits. Each impedance selection circuit can include a first impedance connected to a first interface terminal, a second impedance connected to a second interface terminal, and a plurality of series-connected transistors connected between the first and second impedances. Each impedance selection circuit can also include a plurality of drive impedance networks connected to gates, sources, drains, bodies, and isolation regions of the series-connected transistors, and a control circuit to provide a plurality of control signals to the drive impedance networks to turn on and turn off the series-connected transistors. For each impedance selection circuit, turning on and turning off the respective plurality of series-connected transistors can bring the series combination of the respective first and second impedances into and out of electrical communication with, e.g., into and out of parallel with, the fixed impedance.

Abstract: A line-detection system computes, using a local memory, a result of a partial conversion of image-space pixel data from image space to Hough space. The result is analyzed for edges corresponding to a line present in the partial conversion. The line is compared against other lines detected in previously computed partial results to identify a longest line in the image.

Abstract: An embodiment of a power supply circuit to generate a supply voltage for a gate driver circuit can include an isolated power supply circuit to receive a first voltage in a first isolated system and provide power to a cyclic charging power supply circuit, the cyclic charging power supply circuit providing a supply voltage to the gate driver circuit in a second isolated system, the isolated power supply circuit providing the power to the cyclic charging power supply circuit while the gate driver circuit drives a transistor in an on state. The isolated power supply circuit can include a control circuit to regulate the power provided to maintain or increase the supply voltage while the gate driver circuit drives the transistor in an on state. The power supply circuit can also include the cyclic charging power supply circuit to receive a second voltage in the second isolated system and provide the supply voltage to the gate driver circuit.

Abstract: An integrated device die and package is disclosed. The integrated device die includes a unitary body. The unitary body can have an upper portion comprising one or more active components. The upper portion can have first and second opposing lateral sides defining at least a portion of a periphery of the upper portion such that an upper surface of the upper portion is disposed between upper edges of the first and second opposing lateral sides. The unitary body can also have a lower portion monolithically formed with the upper portion. The lower portion can comprise a pedestal extending downwardly from the upper portion. The pedestal can be laterally inset from lower edges of the first and second opposing lateral sides. The pedestal can include a distal end portion configured to couple to a carrier.

Abstract: An apparatus comprises a switching power circuit and a control circuit. The switching power converter circuit includes an output port for electrical coupling to a variable load, an input port for electrically coupling to a first energy source, wherein the energy density of the first energy source is insufficient to meet a peak energy requirement of the variable load, an input/output port for electrical coupling to a second energy source, and one inductor electrically coupled to the input port and a circuit node, wherein the electrical coupling is non-switchable. The control circuit is configured to charge the inductor using the first energy source via the input port, to provide energy from the inductor to the load via the output port, and to provide both of, via the input/output port, energy from the inductor to the second energy source and energy from the second energy source to the variable load.

Abstract: According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Abstract: A dynamically tunable transconductor includes a voltage-to-current converter stage for generating a current signal based on a voltage signal; and a current scaling stage for scaling the current signal by a scaling factor to achieve a particular transconductance. Current scaling stage includes a coarse tune mechanism having an associated coarse tune step and a fine tune mechanism having an associated fine tune step, where the scaling factor is a ratio of the coarse tune step to the fine tune step. A delta-sigma modulator can implement the transconductor to generate loop filter coefficients by dynamically tuning the transconductance to achieve a particular resistance.

Abstract: A sensor module can include a battery housing comprising a battery cavity sized and shaped to receive a battery. The battery cavity can be defined at least in part by a wall to be disposed about at least a portion of a periphery of the battery. A package housing can be disposed on the wall of the battery housing, the package housing smaller than the battery housing. An integrated device package can be disposed in or coupled with the package cavity. The integrated device package can include one or more integrated device dies. An interfacing feature can be coupled with the battery housing and extending transverse to the wall. The interfacing feature can be configured to transduce a biological signature into a signal to be processed by the integrated device package. An interconnect assembly can electrically connect the interfacing feature to the integrated device package.

Abstract: Present disclosure describes an improved mechanism for addressing component mismatch in a DAC. The mechanism is based on carefully selecting the first DAC unit of an ordered sequence of DAC units that are switched on to convert a particular digital value to an analog value. The mechanism benefits from recognition that selecting the first DAC based on a value of a band-limited dither signal, where the band of the dither signal is selected to be sufficiently removed from the band of the signal of interest, allows shifting effects of DAC units mismatch away from the signal of interest in a manner that is easy to implement and control. Because dither signal is not added to the signal of interest, but is only used to control which DAC units are turned on, drawbacks of a traditional dithering method can be avoided while benefiting from the use of dither.