Patents Assigned to Analog Devices
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Patent number: 9238580Abstract: A MEMS sensor includes a micro-electromechanical structure, a detection circuit, and a self-test circuit to test the health of the MEMS sensor during runtime operations. The self-test circuit is configured to inject into the micro-electromechanical structure a plurality of injected test signals that are broad-band frequency-varying frequency signals, which are based on spread spectrum based modulation. The injected test signals may a magnitude that is below an observable threshold of the sensor signal as well as a test-signal bandwidth that overlaps with a substantial portion of the sensor bandwidth, including the stimulus of interest.Type: GrantFiled: March 11, 2013Date of Patent: January 19, 2016Assignee: Analog Devices GlobalInventors: Kamatchi Saravanan Alagarsamy, William A. Clark, Jishnu Choyi, James M. Lee, Vikas Choudhary
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Patent number: 9241142Abstract: The present disclosure provides a stream processor, an associated stream controller and compiler, and associated methods for data processing, such as image processing. In some embodiments, a method includes defining a kernel pattern associated with an image frame, and processing the image frame using the defined kernel pattern. The method can further include generating a kernel switch lookup table based on the defined kernel pattern. In various implementations, the stream controller is operable to direct execution of kernels on the image frame according to the defined kernel pattern and the kernel switch lookup table.Type: GrantFiled: January 24, 2013Date of Patent: January 19, 2016Assignee: Analog Devices GlobalInventors: Yong Wang, Jianrong Chen, Yimiao Zhao, Youcheng Huang, Xiaoming Chi
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Patent number: 9236880Abstract: The systems, methods, and devices disclosed herein relate to a bit-per-stage ADC. The bit-per-stage ADC extracts one or more bits at each stage and creates a residue so that succeeding similar or identical stages can extract more bits. The ADC uses a reflected binary output code so that a bit can be extracted by observing the sign (e.g., polarity) of an input. The residue can be generated by rectifying the input, multiplying it by two, and level-shifting it by half the span. The generation of the residue is achieved using capacitors and switches. This causes the ADC to have low power consumption and a small size.Type: GrantFiled: April 7, 2015Date of Patent: January 12, 2016Assignee: Analog Devices, Inc.Inventor: John Memishian
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Patent number: 9236841Abstract: An integrated, fully-differential current-feedback transimpedance operational amplifier circuit is disclosed. The circuit can be configured as a class-AB, low-impedance input stage, followed by an inverter-based, rail-to-rail output stage. For enhancing the open-loop transimpedance gain of the amplifier without consuming additional DC power, the same bias current is used both in the input stage and in a gain-enhancement stage serving as its load. The gain-enhancement stage can be either DC- or AC-coupled to the input of the amplifier. In the case of DC coupling, an output common-mode feedback loop can be used to provide the proper operating voltages in the amplifier.Type: GrantFiled: September 19, 2013Date of Patent: January 12, 2016Assignee: Analog Devices, Inc.Inventor: Alexandru A. Ciubotaru
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Patent number: 9235937Abstract: A satellite sensor system includes a base unit and a packaged motion sensor configured to be removably couplable to the base unit. The base unit is configured to mount to a vehicle and to faithfully transmit vehicle motion to an attached sensor.Type: GrantFiled: June 5, 2014Date of Patent: January 12, 2016Assignee: Analog Devices, Inc.Inventor: Harvey Weinberg
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Patent number: 9230751Abstract: Disclosed is a micro-electro-mechanical switch, including a substrate having a gate connection, a source connection, a drain connection and a switch structure, coupled to the substrate. The switch structure includes a beam member, an anchor and a hinge. The beam member having a length sufficient to overhang both the gate connection and the drain connection. The anchor coupling the switch structure to the substrate, the anchor having a width. The hinge coupling the beam member to the anchor at a respective position along the anchor's length, the hinge to flex in response to a charge differential established between the gate and the beam member. The switch structure having gaps between the substrate and the anchor in regions proximate to the hinges.Type: GrantFiled: January 8, 2014Date of Patent: January 5, 2016Assignee: ANALOG DEVICES, INC.Inventors: Denis Ellis, Padraig Fitzgerald, Jo-ey Wong, Raymond Goggin, Richard Tarik Eckl
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Patent number: 9232332Abstract: The disclosed apparatus, systems, and methods provide a calibration technique for calibrating a set of microphones. The disclosed calibration technique is configured to calibrate the microphones with respect to a reference microphone and can be used in actual operation rather than a testing environment. The disclosed calibration technique can estimate both the magnitude calibration factor for compensating magnitude sensitivity variations and the relative phase error for compensating phase delay variations. In addition, the disclosed calibration technique can be used even when multiple acoustic sources are present. The disclosed technique is particularly well suited to calibrating a set of microphones that are omnidirectional and sufficiently close to one another.Type: GrantFiled: July 28, 2014Date of Patent: January 5, 2016Assignee: Analog Devices, Inc.Inventors: Juri Ranieri, David Wingate, Noah Daniel Stein
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Patent number: 9231469Abstract: An apparatus comprises a power converter circuit and a controller. The power converter circuit includes an inductor, a switching circuit, and a digital control loop circuit having an adjustable transfer function, wherein the transfer function includes a zero variable and a signal gain variable. The controller includes a tuning module configured to set a value for the zero variable, set the signal gain variable to a first gain value, determine a control error for the first gain value setting, wherein the control error is a difference between a reference current and a load current at a circuit load, iteratively update the gain value of the signal gain variable and determine the control error for the updated gain value, and set an operating gain value of the signal gain variable to the gain value corresponding to a minimum control error.Type: GrantFiled: October 30, 2013Date of Patent: January 5, 2016Assignee: Analog Devices, Inc.Inventor: Botao Miao
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Patent number: 9231539Abstract: An amplifier, comprising: an input node; an output node; a gain stage having a gain stage inverting input, a gain stage non-inverting input and a gain stage output; a feedback capacitor connected in a signal path between the gain stage output and the gain stage inverting input; a sampling capacitor connected between the input node and the gain stage inverting input, and a controllable impedance in parallel with the feedback capacitor, wherein the controllable impedance is operable to switch between a first impedance state in which it does not affect current flow through the feedback capacitor, and a second impedance state in which it cooperates with the feedback capacitor form a bandwidth limiting circuit.Type: GrantFiled: March 6, 2013Date of Patent: January 5, 2016Assignee: ANALOG DEVICES GLOBALInventors: Colin G. Lyden, Christopher Peter Hurrell, Derek Hummerston
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Patent number: 9232565Abstract: Embodiments of the present invention may provide a receiver. The receiver may include an RF section and a quadrature mixture, coupled to the RF section, to downconvert a first group of wireless signals directly to baseband frequency quadrature signals and to downconvert a second group of wireless signals to intermediate frequency quadrature signals. The receiver may also include a pair of analog-to-digital converters (ADCs) to convert the downconverted quadrature signals to corresponding digital quadrature signals. Further, the receiver may include a digital section having two paths to perform signal processing on the digital baseband frequency quadrature signals and to downconvert the digital intermediate frequency signals to baseband cancelling a third order harmonic distortion therein. The receiver may be provided on a monolithically integrated circuit.Type: GrantFiled: August 14, 2013Date of Patent: January 5, 2016Assignee: ANALOG DEVICES, INC.Inventors: Antonio Montalvo, Kevin G. Gard
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Patent number: 9232333Abstract: The disclosed apparatus, systems, and methods provide a calibration technique for calibrating a set of microphones. The disclosed calibration technique is configured to calibrate the microphones with respect to a reference microphone and can be used in actual operation rather than a testing environment. The disclosed calibration technique can estimate both the magnitude calibration factor for compensating magnitude sensitivity variations and the relative phase error for compensating phase delay variations. In addition, the disclosed calibration technique can be used even when multiple acoustic sources are present. The disclosed technique is particularly well suited to calibrating a set of microphones that are omnidirectional and sufficiently close to one another.Type: GrantFiled: July 28, 2014Date of Patent: January 5, 2016Assignee: Analog Devices, Inc.Inventors: Juri Ranieri, David Wingate, Noah Daniel Stein
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Patent number: 9231614Abstract: The present disclosure describes a mechanism to digitally correct for the static mismatch of the digital-to-analog converter (DAC) in at least the first-stage of a multi-stage noise shaping (MASH) analog-to-digital converter (ADC). The correction is applicable to continuous-time implementations, and is especially attractive for high-speed applications.Type: GrantFiled: June 6, 2014Date of Patent: January 5, 2016Assignee: Analog Devices, Inc.Inventors: Jose Barreiro Silva, Jialin Zhao, Wenhua W. Yang
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Publication number: 20150381146Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.Type: ApplicationFiled: May 5, 2014Publication date: December 31, 2015Applicant: Analog Devices, Inc.Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
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Publication number: 20150378939Abstract: A memory mechanism for providing semaphore functionality in a multi-master processing environment is disclosed. An exemplary memory unit includes a memory controller that manages access to a shared memory. The memory controller includes a semaphore context monitor associated with each master having access to the shared memory. A semaphore context monitor associated with a semaphore-capable master is activated by the semaphore-capable master (for example, by exclusive request signal(s) received by memory controller from semaphore-capable master). A semaphore context monitor associated with a non-semaphore-capable master is activated by the memory controller (for example, by exclusive request signal(s) generated by the memory controller).Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Applicant: ANALOG DEVICES, INC.Inventor: Ahmed Ali Mohamed
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Publication number: 20150381128Abstract: A hybrid, translinear amplifier has at least one gain stage including first and second gain transistors, at least a first load transistor electrically coupled to the first gain transistor and at least a second load transistor electrically coupled to the second gain transistor, and load resistors electrically coupled to the load transistors. A hybrid, translinear amplifier with selectable gain has a first hybrid, translinear amplifier cell having at least first and second load transistors, each load transistor having a load resistor, at least one additional hybrid, translinear amplifier cell having at least third, fourth, fifth and sixth load transistors, each load transistor having a load resistor, at least two switches electrically coupled to the amplifier cells to allow selection of one of the amplifier cells, and a differential output signal having a gain corresponding to a selected amplifier cell.Type: ApplicationFiled: February 27, 2014Publication date: December 31, 2015Applicant: Analog Devices, Inc.Inventor: Barrie Gilbert
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Publication number: 20150372682Abstract: An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.Type: ApplicationFiled: June 19, 2015Publication date: December 24, 2015Applicant: ANALOG DEVICES, INC.Inventors: ALEXANDER A. ALEXEYEV, ERIC G. NESTLER
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Patent number: 9217766Abstract: A device and method for measuring active and reactive powers of an alternating current includes receiving a first signal representing a current and a second signal representing a voltage, in which the current includes a phase offset with respect to the voltage, calculating an active power and reactive power based on the first and second signals, and calibrating the calculated active and reactive powers with respect to the phase offset using first and second constants, in which the first and second constants respectively correspond to a sine value and a cosine value of the phase offset.Type: GrantFiled: August 17, 2011Date of Patent: December 22, 2015Assignee: ANALOG DEVICES, INC.Inventors: Gabriel Antonesei, Jianbo He
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Patent number: 9218015Abstract: Circuits for generating a PTAT voltage as a base-emitter voltage difference between a pair of bipolar transistors. The circuits may form unit cells in a cascading voltage reference circuit that increases the PTAT voltage with each subsequent stage. The bipolar transistors are controlled using a biasing arrangement that includes an MOS transistor connected to a current mirror that provides the base current for the bipolar transistors. A voltage reference is formed by combining a PTAT voltage and a CTAT voltage at the last stage. The voltage reference may be obtained from the voltage at an emitter of one of the bipolar transistors in the last stage.Type: GrantFiled: October 10, 2012Date of Patent: December 22, 2015Assignee: ANALOG DEVICES, INC.Inventor: Stefan Marinca
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Patent number: 9219410Abstract: A voltage generator may include a plurality of charge pumps, plural sets of delay pipelines and a phase controller. Given M delay pipelines having N stages each, there may be M*N charge pumps each having a triggering input coupled to a respective stage or a respective pipeline. The phase controller may include a plurality of phase control stages interconnecting among the delay pipelines to induce timing offsets among the outputs of the delay stage. In an alternate design, intermediate nodes among the pipeline's delay stages may be coupled to triggering inputs of a sub-set of the charge pumps. The phase controller may have a plurality of phase control stages coupled, respectively, between the intermediate nodes of the delay pipeline and intermediate nodes of the phase control stages may be coupled to triggering inputs of another sub-set of the charge pumps.Type: GrantFiled: September 14, 2012Date of Patent: December 22, 2015Assignee: ANALOG DEVICES, INC.Inventors: Jipeng Li, Richard E. Schreier
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Patent number: 9219414Abstract: A switching regulator or other apparatus or techniques can include load current monitoring to provide a digital representation of an estimated load current. Load current monitoring can be performed by a circuit including a counter circuit, a comparator circuit, and a digitally-controlled source coupled to the counter circuit and configured to adjust a bias condition of a sensing device in response to a count provided by the counter circuit in order to establish a proportional relationship between a current conducted by the sensing device and a corresponding current conducted by a power switching device. The counter circuit is configured to increment and decrement the count in response to information provided by the comparator output and the count is generally indicative of the estimated load current, such as an average load current.Type: GrantFiled: October 28, 2013Date of Patent: December 22, 2015Assignee: Analog Devices GlobalInventor: Bin Shao
