Abstract: The circuit of the present disclosure is a high-speed precision clamp (voltage limiter) for overvoltage or undervoltage protection. One aspect of the circuit includes using a peak detector in the feedback path of a clamp having a super-diode architecture. The resulting circuit performs well for high-speed applications. The peak detector can be replicated (at least in part) to accommodate a multiplicity of phase-shifted input voltages by using only one common peak detection capacitor and ensuring area savings in integrated-circuit implementations.

Abstract: According to one example, a digital phase detector is disclosed for use with a phase lock loop. The digital phase detector is configured to operate in a low-frequency environment and to filter noise and transients in a signal, while also being tolerant of dropped phase pulses. In some embodiments, the digital phase detector is configured to measure up to two REFCLK edges with respect to a FBCLK signal, and if an edge occurs in the first half of REFCLK, classify the edge as lagging, and if an edge occurs in the second half of REFCLK, classify the edge as leading. If both edges are leading or both are lagging, the smaller of the two is used as the phase. If one is leading and one is lagging, the difference is used as the phase.

Abstract: An electrical circuit includes a sensor configured to generate a current signal comprising a first portion comprising a contribution from a target source and/or a second portion comprising a contribution from sources other than the target source, a trans-impedance amplifier that amplifies the current signal and generate a low noise signal, and a high pass filter that converts the low noise signal into an AC signal having a positive amplitude, a negative amplitude, and a zero cross-over point between the positive and negative amplitudes. The circuit also includes a positive integrating amplifier that receives the positive amplitude of the AC signal and generates a positive integrated value over an integration period, and a negative integrating amplifier that receives the negative amplitude of the AC signal and generates a negative integrated value over the integration period. The circuit further includes at least one analog-to-digital converter that receives the integrated values.

Abstract: A method for detecting a preamble in a received radio signal includes demodulating the radio signal based on a carrier derived from a local timing source to provide a digital signal including a sequence of bits oscillating at approximately a modulated data rate. A bit width of each successive bit of the digital signal is determined. If a pair of consecutive bit widths has a combined width within a threshold, the bit pair is indicated as potentially belonging to a preamble. If a threshold number of potential preamble bit pairs in a sequence of bit pairs within a given window is detected, the sequence of bit pairs is indicated as potentially belonging to a preamble. A measure of bit widths of at least some bits within a sequence of preamble bit pairs can be provided and a frequency of the local timing source can be adjusted according to the measure.

Abstract: Example embodiments of this disclosure can provide an apparatus, a system, and a method of correcting for charge lost from a sampling capacitor as a result of an analog to digital conversion being performed. In an embodiment, there is provided a method of operating an analog to digital converter comprising at least a first sampling capacitor used to sample an input signal, where the method can further comprise a correction step of modifying the voltage across the at least first sampling capacitor, the correction step being performed prior to commencing an acquire phase.

Abstract: The present disclosure relates to a method and apparatus for generating a voltage reference. More particularly the present disclosure relates to a methodology and circuitry configured to provide an output signal that combines a proportional to absolute temperature component with a complimentary to absolute temperature component to generate a stable output which is not temperature dependent.

Abstract: A magnetic field energy harvesting device may include an inductor and a controller. The inductor may include two inductor windings connected to each other in series, configured in winding directions and orientations to generate two voltages relative to the middle tap of inductor and out of phase with each other. The controller may switch the two voltages and may generate an approximately constant DC output voltage by alternating switching on and off switches.

Abstract: A protection circuit including a multi-gate high electron mobility transistor (HEMT), a forward conduction control block, and a reverse conduction control block is provided between a first terminal and a second terminal. The multi-gate HEMT includes an explicit drain/source, a first depletion-mode (D-mode) gate, a first enhancement-mode (E-mode) gate, a second E-mode gate, a second D-mode gate, and an explicit source/drain. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward conduction control block turns on the second E-mode gate when a voltage difference between the first and second terminals is greater than a forward conduction trigger voltage, and the reverse conduction control block turns on the first E-mode gate when the voltage difference is more negative than a reverse conduction trigger voltage.

Abstract: Embodiments of the present invention may provide a signal processing circuit that may comprises an analog-to-digital converter (ADC), and an output restriction circuit. The output restriction circuit may reduce the accuracy of the digital output of the ADC when signal content exceeds a pre-determined spectrum mask in an undesirable band. In one embodiment, the input signal spectrum may be actively monitored and when the input spectrum is inconsistent with an intended application, the output resolution may be restricted, for example, by truncating least significant bits (LSBs) of the digital output or adding digital noise.

Abstract: A transmission system may include a transformer, an adder, an encoder, and a transmitter. The transformer may segment and transform a data packet into segments. The adder may add a check code to each of the segments. The encoder may encode error correction to each of the segments with the added check code. A receiving system may include a receiver, a decoder, a checker, and a selector decoder. The decoder may decode error correction in each of the encoded segments. The checker may check the check code of the error corrected segments. The selector decoder may select at least one of the valid segments based upon the check code and transform the selected segments into a data packet.

Abstract: Apparatus and methods for clock and data recovery (CDR) are provided herein. In certain configurations, a first CDR circuit captures data and edge samples from a first input data stream received over a first lane. The data and edge samples are used to generate a master phase signal, which is used to control a phase of a first data sampling clock signal used for capturing the data samples. Additionally, the first CDR circuit generates a master phase error signal based on changes to the master phase signal over time, and forwards the master phase error signal to at least a second CDR circuit. The second CDR circuit processes the master phase error signal to generate a slave phase signal used to control a phase of a second data sampling clock signal used for capturing data samples from a second input data stream received over a second lane.

Abstract: An analog-to-digital converter system that includes a pipeline of successively-cascaded signal converters, each operating alternatively in a first circuit configuration and a second circuit configuration, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system.

Abstract: A power delivery system is disclosed for an isolated measurement system in which a power transmitter and power receiver are provided at powered and unpowered sides of an isolation barrier, respectively. The power transmitter and power receiver may be coupled by an isolator. The power transmitter may deliver power to the power receiver to power components on the unpowered side of the isolation barrier. The system may include a controller provided in the powered side to generate a clock signal defining timing of a predetermined operation of the measurement system and to generate a disabling signal to the power transmitter controller synchronously with the timing of the predetermined operation.

Abstract: A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.

Abstract: A bulk acoustic wave gyroscope has a primary member in a member plane, and an electrode layer in an electrode plane spaced from the member plane. The electrode layer has a first portion that is electrically isolated from a second portion. The first portion, however, is mechanically coupled with the second portion and faces the primary member (e.g., to actuate or sense movement of the primary member). For support, the second portion of the electrode is directly coupled with structure in the member plane.

Abstract: A method for measuring retained surface charges within a MEMS device includes performing an initial voltage sweep on the MEMS device, and recording the capacitance between a first and second electrode of the MEMS device. The method may then (1) apply a stress signal to the MEMS device that causes a first and/or second electrode within the MEMS device to retain a surface charge, and (2) perform at least one additional voltage sweep on the MEMS device. The method may record the capacitance during the additional voltage sweep(s), and calculate a C-V center voltage shift based upon the data obtained during the initial voltage sweep and additional voltage sweep. The voltage shift is representative of the retained surface charge.

Abstract: Apparatus and methods for ultrasound transmit switching are provided. In certain implementations, a transmit switch includes a bias polarity control circuit, a bias circuit, a first high voltage field effect transistor (HVFET), and a second HVFET. The sources of the first and second HVFETs are connected to one another at a source node, the gates of the first and second HVFETs are connected to one another at a gate node, and the drains of the first and second HVFETs are connected to an input terminal and an output terminal, respectively. The bias circuit and the bias polarity control circuit are each electrically connected between the source node and the gate node. The bias polarity control circuit can turn on or off the HVFETs by controlling a polarity of a bias voltage across the bias circuit, such as by controlling a direction of current flow through the bias circuit.

Abstract: A switched-mode power conversion circuit can include a switch control circuit including switch control outputs coupleable to switches included in a bridge network, the switches controllably coupling power input nodes to an isolation transformer according to switch states established by the switch control circuit. A current monitoring circuit can be coupled to the isolation transformer, the current monitoring circuit including an output indicative of a current flowing through a winding of the isolation transformer. A sampling circuit can be coupled to the output of the current monitoring circuit to obtain information indicative of a first current peak during a first sampling duration corresponding to a first current polarity established by the bridge network and a second current peak during a second sampling duration corresponding to an opposite second current polarity established by the bridge network.

Abstract: In one aspect, there is disclosed a digital signal processor and method performed by the same for performing object detection, including facial detection, in a reduced number of clock cycles. The method comprises using Sobel edge detection to identify regions with many edges, and classifying those regions as foreground candidates. Foreground candidates are further checked for vertical or horizontal symmetry, and symmetrical windows are classified as face candidates. Viola-Jones type facial detection is then performed only on those windows identified as face candidates.

Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (??) modulator is provided at the front-end of the MASH ADC, and another full ?? modulator is provided at the back-end of the MASH ADC. The front-end ?? modulator digitizes an analog input signal, and the back-end ?? modulator digitizes an error between the output of the front-end ?? modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.