Abstract: An array of microbumps with a layer or coating of non-superhydrophobic material yields a superhydrophobic surface, and may also have a contact angle hysteresis of 15 degrees or less. A surface with such an array may therefore be rendered superhydrophobic even though the surface structure and materials are not, by themselves, superhydrophobic.

Abstract: An amplifier system has an amplifier for amplifying a plurality of input signals from a plurality of different channels, and a plurality of demodulators each operatively coupled with the amplifier for receiving amplified input signals from the amplifier. Each demodulator is configured to demodulate a single amplified input channel signal from a single channel of the plurality of different channels. The system thus also has a plurality of filters, coupled with each of the demodulators, for mitigating the noise.

Abstract: Backside recesses in a base member host components, such as sensors or circuits, to allow closer proximity and efficient use of the surface space and internal volume of the base member. Recesses may include covers, caps, filters and lenses, and may be in communication with circuits on the frontside of the base member, or with circuits on an active backside cap. An array of recessed components may a form complete, compact sensor system.

Abstract: A MEMS system has an input for receiving a plurality of frequency division multiplexed variable capacitance signals, and a readout node electrically coupled with the input. Each variable capacitance signal is produced by a variable capacitor and has data relating to movement of microstructure associated with that variable capacitor. Moreover, each variable capacitance signal is produced by a variable capacitor that is different from the variable capacitor producing any of the other variable capacitance signals. The system further has a mixer electrically coupled with the readout node, and an output electrically coupled with the mixer. The mixer is configured to substantially continuously receive the plural variable capacitance signals. In addition, the output has an output interface for delivering the plurality of variable capacitance signals in parallel. The signals at the output should represent real time signals, as compared to stale sample and hold signals used in prior art systems.

Abstract: A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.

Abstract: A calibration system for a MEMS system having at least one overdamped motion axis includes a measurement module for determining a location of a pole of a MEMS device in the overdamped motion axis, a closed-loop feedback system configured to change a first location of the pole to a second location of the pole, and a computation module for calculating a resonant frequency and/or a quality factor using the first and the second location of the pole as determined by the measurement module. The calibration system further includes a calibration module for calibrating the MEMS system based on the calculated resonant frequency and/or the calculated quality factor.

Abstract: An apparatus and method for high voltage transient electrical overstress protection are disclosed. In one embodiment, the apparatus includes an internal circuit electrically connected between a first node and a second node; and a protection circuit electrically connected between the first node and the second node. The protection circuit is configured to protect the internal circuit from transient electrical overstress events while maintaining a relatively high holding voltage upon activation.

Abstract: A circuit, system, machine-readable storage medium and method for detecting the leakage impedance in a voltage source is described. The method for identifying a presence of a leakage path in a multi-cell floating voltage source may include supplying a current to a node of the floating voltage source and sampling the voltage of the floating voltage source using a pair of amplifiers connecting in inverting configurations. The method may include sampling a reference ground potential using a reference amplifier connected in an inverting configuration. Each of the amplifiers may output an output signal. The method may include adjusting the current supplied to the node of the floating voltage source and resampling the voltage of the floating voltage source and the reference ground potential. The value of the leakage impedance may be calculated using the sampled and resampled values. The measurements may be performed independent of the battery voltage.

Abstract: Embodiments of the present invention may provide a clock and timing generation scheme for a video signal processor (e.g., a scaler), which enables fast switching between different input video standards without disturbing the output clock or timing. The scheme also may minimize the number of video frames that are dropped or repeated at the output. This may be achieved by locking the video's output timing to the input timing and also by utilizing a frame buffer to remove instantaneous discontinuities caused when an input is changed.

Abstract: Transmitter signals are modulated with one or more codes which may represent a pulse even though the code(s) are not shaped as pulses. The code(s) may be generated by defining a pulse by its Fourier components, and then adding random phases to the Fourier components. A time-domain signal may then be created, which may serve as the code to be modulated on a carrier wave. Upon reflection of the transmitter signal, the received signal may be processed by a receiver to recover the pulse. The time-of-flight of the transmitter signal can then be determined, enabling distance measurements to be made.

Abstract: A digital PLL may be combined with an analog PLL so that the output of the digital PLL is at a frequency high enough to maintain stability in the analog PLL when an initial reference clock signal is too low to maintain stability in the analog PLL. The digital PLL may include a scaling circuit, such as a frequency divider in the feedback path of the PLL, to generate the higher frequency output signal from the lower frequency reference input signal. The digital PLL may also use an on-chip free run ring oscillator as the clock for the digital PLL engine.

Abstract: Apparatus and methods are disclosed, such as those involving a junction field effect transistor for voltage protection. One such apparatus includes a protection circuit including an input, an output, and a JFET. The JFET has a source electrically coupled to the input, and a drain electrically coupled to the output, wherein the JFET has a pinch-off voltage (Vp) of greater than 2 V in magnitude. The apparatus further includes an internal circuit having an input configured to receive a signal from the output of the protection circuit. The protection circuit provides protection over the internal circuit from overvoltage and/or undervoltage conditions while having a reduced size compared to a JFET having a Vp of smaller than 2 V in magnitude.

Abstract: An interface circuit for controlling a cross-domain signal link between a first circuit domain and a second circuit domain in a circuit may include first and second controllers, each of the first and second controllers including a first input coupled to a first voltage source of the first circuit domain and a second input coupled to a second voltage source of the second circuit domain.

Abstract: Some general aspects relate to systems and methods of analog computation using numerical representation with uncertainty. For example, a specification of a group of variables is accepted, with each variable having a set of at least N possible values. The group of variables satisfies a set of one or more constraints, and each variable is specified as a decomposition into a group of constituents, with each constituent having a set of M (e.g., M<N) possible constituent values that can be determined based on the variable values. The method also includes forming a specification for configuring a computing device that implements a network representation of the constraints based on the specification of the group of variables. The network representation includes a first set of nodes corresponding to the groups of constituents, a second set of nodes corresponding to the set of constraints, and interconnections between the first and the second sets of nodes for passing continuous-valued data.

Abstract: Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

Abstract: Embodiments of the present invention provide improved accuracy of displacement control by using a multi-segment transformation of an actuator's non-linear response. The present invention may set intermediate points to effectively divide the actuator response into multiple segments. Each segment may be assigned a transform function that represents the actuator's response in that particular segment. The present invention may operate in two modes, a calibration mode and a normal operations mode. During calibration mode, the intermediate points and the segment transforms may be set. During normal operations mode, a drive signal may be generated according to the calibrated set values.

Abstract: A tracking module that tracks the operation of a digital-to-analog converter (DAC). The DAC tracking module may be included on-chip with a DAC, and be formed with similar circuit components as a DAC. The DAC tracking circuit may output a signal indicating that the DAC within a SAR ADC has settled to an approximate value during each bit conversion. A differential solution is also provided. Power may be optimized because optimal conversion speed may be achieved, and a comparator within the DAC may be turned off or placed in a standby mode at the end of bit conversions, and before the next conversion cycle in response to the signal output by the DAC tracking module.

Abstract: A micromachining process forms a plurality of layers on a wafer. This plurality of layers includes both a support layer and a given layer. The process also forms a mask, with a mask hole, at least in part on the support layer. In this configuration, the support layer is positioned between the mask hole and the given layer, and longitudinally spaces the mask hole from the given layer. The process also etches a feature into the given layer through the mask hole.

Abstract: A low voltage driver for a higher voltage LCD includes a plurality of LCD drive bias voltage input-terminals; an LCD drive voltage output terminal; an input transistor switching circuit having at least one switch for each LCD drive bias voltage for selecting one of the bias voltages; an output transistor switching circuit, responsive to the input transistor switching circuit, for applying the selected one of the bias voltages to the LCD drive voltage output terminal, the transistors of the switching circuits having a predetermined breakdown voltage; a level shifter for providing switching voltages counterpart to the plurality of bias voltages; a logic circuit for enabling the first transistor switching circuit to select a one of the bias voltages and applying a set of counterpart switching voltages to the input and output transistor switching circuits for connecting the selected one of the bias voltages to the output terminal and applying a set of switching voltages to the input and output switching circuits

Abstract: A stage of a pipelined analog-to-digital converter can include first and second pluralities of digital-to-analog converters (DACs), the first plurality sufficient in number to produce a residue from the stage, the second plurality having their outputs added into an analog output of the stage. A mapping circuit can exchange inputs between selected ones of the first and second pluralities of DACs, and a calibration circuit can provide first and second calibration signals to the selected one of the first plurality and another of the second plurality of DACs. The calibration signals can correlate to each other, but be uncorrelated to an analog input and digital output of the stage, and have unequal and partially offsetting effects on the stage's residue. A correction circuit can correct the digital output of the stage for circuit path errors based on a correlation between the calibration signals and an output of a succeeding stage.