Abstract: A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping.

Abstract: An amplifier system can include a feedback amplifier circuit having an amplifier, a feedback capacitor connected between an input terminal and an output terminal of the amplifier by at least one first switch, and a reset capacitor connected across the feedback capacitor by at least one second switch and between a pair of reference voltages by at least one third switch. During an input-signal processing phase of operation, a control circuit may close the at least one first switch and open the at least one second switch to electrically connect the feedback capacitor between the input and output terminals to engage feedback processing by the feedback amplifier circuit, and close the third switch to electrically connect the reset capacitor between the first and second voltages to charge the reset capacitor to a selectable voltage difference.

Abstract: A semiconductor die with an integrated electronic circuit, configured so as to be mounted in a housing with a capacitive transducer e.g. a microphone. A first circuit is configured to receive an input signal from the transducer at an input node and to provide an output signal at a pad of the semiconductor die. The integrated electronic circuit comprises an active switch device with a control input, coupled to a pad of the semiconductor die, to operatively engage or disengage a second circuit interconnected with the first circuit so as to operate the integrated electronic circuit in a mode selected by the control input. That is, a programmable or controllable transducer. The second circuit is interconnected with the first circuit so as to be separate from the input node. Thereby less noise is induced, a more precise control of the circuit is obtainable and more advanced control options are possible.

Abstract: An uncalibrated converter element in an analog-digital converter may be replaced with two or more smaller elements having an effective total net value that is equal to that of the uncalibrated converter element. In an exemplary case where the element is capacitor, one or more of these smaller capacitors may be independently calibrated by switching the smaller capacitor between two voltages, such as a reference voltage and ground, and then calculating a difference of corresponding digital output codes generated by the backend ADC with previously calibrated capacitors associated with lesser significant bits. The total capacitance of the uncalibrated capacitor may be apportioned between the smaller capacitors so that the individual maximum charge contribution of each smaller capacitor to the converter output together with any expected manufacturing variance does not exceed the aggregated contribution of the previously calibrated capacitors.

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Abstract: Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.

Abstract: Fault detection techniques for control of sensor systems. A sensor control integrated circuit (“IC”) may include a fault detection system for coupling to the sensor supply lines. The system may detect faults for each of the sensor supply lines. The fault detection system may level shift sensor supply line signals from a first voltage domain to a second voltage domain appropriate for the fault detection system of the controller IC. The fault detection system may level shift source potential voltages from the first voltage domain to the second voltage domain to detect predetermined fault types. The fault detection system may compare the second domain voltages from the sensor supply lines to voltages representing predetermined fault types and may generate fault status indicators based on the comparison.

Abstract: An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. Configurations are disclosed for analog and digital input signals.

Abstract: Apparatus and methods for reducing output noise of a signal channel are provided. In one embodiment, a signal channel includes an amplifier for amplifying an input signal to generate an amplified signal. The amplifier includes a bias circuit that controls a bias current of the amplifier based on a voltage across a biasing capacitor. The apparatus further includes a sampling circuit for sampling the amplified signal. The sampling circuit generates an output signal based on a difference between a first sample of the amplified signal taken at a first time instance and a second sample of the amplified signal taken at a second time instance. The bias circuit samples a bias voltage onto the biasing capacitor before the first time instance and holds the voltage across the biasing capacitor substantially constant between the first time instance and the second time instance to reduce noise of the output signal.

Abstract: Harsh electrical environments integrated circuit protection for system-level robustness and methods of forming the same are provided. In one embodiment, a protection system includes dual-polarity high blocking voltage primary and secondary protection devices each electrically connected to a pad. The primary protection device has a current handling capability greater than a current handling capability of the secondary protection devices, and the secondary protection device has a turn-on speed that is faster than a turn-on speed of the primary protection device so as to decrease pad voltage overshoot when a fast transient electrical event occurs on the pad. Additionally, the holding voltage of the primary protection device is less than a holding voltage of the secondary protection device such that once the primary protection device has been activated the primary protection device clamps the pad voltage so as to minimize a flow of high current through the secondary protection device.

Abstract: A clock distribution system for a multi-bit latch. The clock distribution system may include a plurality of branches, each connected to a common clock input. Each branch may be driven by an input clock buffer. Each branch may be connected to clock inputs of a predetermined number of latch stages within the multi-bit latch. A predetermined number of clock branches may include a clock output buffer. The number of clock output buffers may be less than the total number of latch stages. In this manner the clock distribution system may reduce the feed through capacitance of the latch stages, which may mitigate the latch transition skew for each latch stage.

Abstract: An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The method also reads each memory location to verify that the memory location is unprogrammed and activates the programming circuitry for each memory location, which applies a test current to the programming circuitry. The test current is less than a threshold current needed to permanently change the state of the circuit element. The method then determines whether the programming circuitry is functioning properly.

Abstract: A method of bonding wafers with an aluminum-germanium bond includes forming an aluminum layer on a first wafer, and a germanium layer on a second wafer, and implanting the germanium layer with non-germanium atoms prior to forming a eutectic bond at the aluminum-germanium interface. The wafers are aligned to a desired orientation and the two layers are held in contact with one another. The aluminum-germanium interface is heated to a temperature that allows the interface of the layers to melt, thus forming a bond. A portions of the germanium layer may be removed from the second wafer to allow infrared radiation to pass through the second wafer to facilitate wafer alignment.

Abstract: A continuous-rate clock and data recovery circuit includes a delay locked loop with a first integrator and a phase locked loop with a separate integrator. The delay locked loop and the phase locked loop are in a dual loop architecture. The first integrator is a digital accumulator that wraps upon exceeding a maximum or minimum value. The second integrator is a digital accumulator that saturates at its maximum or minimum value.

Abstract: An architecture of an integrated circuit allows for the canceling of noise sampled on a capacitor in the integrated circuit, after an input signal has already been sampled. Thermal noise correlated with an arbitrary input signal may be canceled after selectively controlling a plurality of switching devices during a sequence of clock phases. An auxiliary capacitor may be used to store a voltage equal to the thermal noise and enable the cancellation of the thermal noise from the sampled signal in conjunction with a noise cancellation unit.

Abstract: Methods and an apparatus are provided for interpolation of pixels in a pixel array having rows and columns of pixels. The apparatus includes a shift register array to shift pixel values of the pixel array, the shift register array including two or more shift registers; an interpolation filter array interconnected to the shift register array, the interpolation filter array including one or more interpolation filters; and a controller configured to provide pixel values in columns of the pixel array from the shift register array to respective interpolation filters in a first mode and configured to provide pixel values in rows of the pixel array from the shift register array to respective interpolation filters in a second mode. The controller may be configured to supply vertical sub-pixel values from the shift register array to the interpolation filters to generate diagonal sub-pixel values.

Abstract: As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point.

Abstract: An I/Q imbalance compensation block of a RF receiver for compensating an imbalance between an in-phase component and a quadrature component of an RF signal is disclosed. The compensation block includes a conjugation block; an adaptive finite impulse response (FIR) filter; and an adder. The filter use filter coefficients iteratively updated at least partly in response to a compensated digital signal. The filter can have a complex number for at least one, but not all of filter taps, and real numbers for other filter taps. The filter can be provided with adaptation step sizes different from filter tap to filter tap. The filter can also be provided with an adaptation step size(s) varying over time. The filter can also be provided with an adaptation step size(s) divided by the square norm of the compensated signal.

Abstract: A MEMS device has a first member that is movable relative to a second member. At least one of the first member and the second member has exposed silicon carbide with a water contact angle of greater than about 70 degrees.

Abstract: A voltage reference circuit comprises a plurality of ?VBE cells, each comprising four bipolar junction transistors (BJTs) connected in a cross-quad configuration and arranged to generate a ?VBE voltage. The plurality of ?VBE cells are stacked such that their ?VBE voltages are summed. A last stage is coupled to the summed ?VBE voltages and arranged to generate one or more VBE voltages which are summed with the ?VBE voltages to provide a reference voltage. This arrangement serves to cancel out first-order noise and mismatch associated with the two current sources present in each ?VBE cell, such that the voltage reference circuit provides ultra-low 1/f noise in the bandgap voltage output.