Abstract: In one aspect, a method of reducing power consumption in a circuit by adaptive bias current generation of a bias current configured to bias, at least in part, at least one amplifier of the circuit is provided. The method comprises establishing the bias current based, at least in part, on a reference frequency of a reference clock providing a clock signal to at least one component of the circuit, and changing the bias current in response to a change in the reference frequency of the at least one reference clock, the bias current being change non-linearly with respect to the change in the reference frequency of the at least one reference clock. In another aspect, the method comprises establishing the bias current based, at least in part, on a capacitance of a reference capacitor, and changing the bias current in response to a change in the capacitance of the reference capacitor such that the bias current is changed non-linearly with respect to changes in the capacitance of the reference capacitor.

Abstract: The proper operation of a phase locked loop is determined by monitoring certain signals within the loop for their phase relationship or duty cycle. If a malfunction of the loop is detected, proper operation may be imposed or restored by resetting a phase-frequency detector, or by flipping the output of the phase-frequency detector.

Abstract: Variable attenuation systems having continuous input steering may be used to implement vector or quadrature modulators and vector multipliers. Discrete implementations of attenuators with continuous input steering may have two outputs which may be cross-connected to provide four-quadrant operation. A symmetrically driven center tap may provide improved zero-point accuracy.

Abstract: A pipeline analog to digital converter comprising: a first analog to digital converter for determining a first part of an analog to digital conversion result, and for forming a residue signal; an amplifier for amplifying the residue signal, the amplifier including at least one offset sampling capacitor for sampling an offset of the amplifier, wherein at least one resistance is associated with the at least one capacitor so as to form a filter, and the at least one resistor is variable such that an amplifier bandwidth can be switched between a first bandwidth and a second bandwidth less than the first bandwidth during sampling of the offset.

Abstract: Embodiments of the present invention provide an apparatus and control method for an analog front end (AFE) amplifier for controlling DC restore operations. According to the exemplary method, a first input stage of the AFE is controlled to operate as a continuous time amplifier that has high input impedance and draws substantially no input leakage current for a first predetermined area of an imaging sensor image array. The first input stage is controlled to operate as a sample and hold amplifier with DC restore functionality for a second predetermined area of the imaging sensor image array. According to an embodiment, the AFE input stage operates as a continuous time amplifier when reading pixels from the sensor's active image array but operates as a sample and hold amplifier with DC restore when reading pixels from the image array that correspond to so-called ‘black-level’ pixels or pixels that otherwise fall outside the sensor's active image field.

Abstract: An integrated circuit includes a micromachined transducer and a charge pump. More particularly, on one silicon substrate, a control circuit delivers high voltage from the charge pump to operate the transducer. An electronic apparatus, such as a cell phone or automatic test equipment may include such an integrated circuit.

Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas.

Abstract: An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector A [N?1:0] and a second N-bit vector B[N?1:0] in the digital logic circuit, where N is a non-zero positive number. A third N-bit vector is then obtained by performing a bit-wise AND (A [N?1:0] & ˜B[N?1:0]) operation using A[N?1:0] and ˜B[N?1:0]. Further, a fourth N-bit vector is obtained by performing a bit-wise XOR (A[N?1:0]^˜B[N?1:0]) operation using A[N?1:0] and ˜B[N?1:0]. The difference between the first N-bit vector A[N?1:0] and the second N-bit vector B[N?1:0] is then declared as equal to a given number or to be within a given range of two numbers (+m and +n, m<n) based on bit patterns in the third N-bit vector and the fourth N-bit vector.

Abstract: A microchip has a bonding material that bonds a first substrate to a second substrate. The bonding material has, among other things, a rare earth metal and other material.

Abstract: A microchip has a bonding material that bonds a first substrate to a second substrate. The bonding material has, among other things, a rare earth metal and other material.

Abstract: An input bias current cancellation circuit includes reference transistors placed in series and a current summation network. The current summation network can be configured to sum the base currents of the reference transistors to produce a summed current. A current mirror can be provided to attenuate the summed current to produce input bias cancellation currents. The input bias cancellation currents can be provided to the base inputs of an input bipolar differential pair, thereby reducing input current noise.

Abstract: Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an actively-controlled protection circuit includes a detector, a timer, a current source and a latch. The detector is configured to generate a detection signal when the detector determines that a transient signal satisfies a first signaling condition. The timer is configured to receive the detection signal, and to generate a current control signal. The current control signal is provided to a current source, which produces a trigger current at least partly in response to the control signal. The trigger current is provided to a node of the latch, thereby enhancing the conductivity modulation of the latch and selectively controlling the activation voltage of the latch.

Abstract: The present application relates to the manufacture of Wafer Level Chip Scale Packages (WLCSPs), which are a type of CSP in which the traditional wire bonding arrangements are dispensed with in favor of making direct contact by means of conductive bumps (typically solder balls) to the integrated circuitry. WLCSPs differ from fine pitch Ball Grid Array (BGA) and leadframe based Chip Scale Packages (CSPs) in that most of the packaging process steps are performed at wafer level. A package and method of manufacture are provided which prevent the ingress of light to the internal circuitry of WLCSP packages by providing a substantially opaque coating on the inactive side of the WLCSP packages and at least partially on the sides of WLCSP packages.

Abstract: A multi-voltage biasing system with over voltage protection has an amplifier with a stage including at least one output device and one cascode protection device having a predetermined maximum recommended voltage; a biasing network is selectively responsive to a plurality of different supply voltages at least one of which is higher than the maximum recommended voltage for providing to the stage a bias voltage to operate the cascode device and output device below their maximum recommended voltages.

Abstract: A serial protocol and interface for data transmission from a data transmitter 12 to a data receiver 14 where the propagation delay may be up to several clock cycles long and may be varying slowly. The data receiver provides a clock to the data transmitter. A synchronization signal provided by either the receiver or the transmitter initiates a frame of data transmission at a transfer rate controlled by the clock. The synchronization signal coordinates the transmission of a data header followed by a predetermined number of data bits, known as the frame length. The data receiver uses the header bits to determine the times to sample the subsequent data bits. The length of the frame is limited to provide sufficient likelihood the propagation delay line characteristics have not changed enough to cause a bit error. The system resynchronizes at the beginning of each frame.

Abstract: Embodiments of the present invention provide a hybrid analog to digital converter that may include a DAC coupled to a hybrid analog to digital converter input; an integrator having an input coupled to the hybrid analog to digital converter input and the DAC, and generating an integrator output; a comparator coupled to the integrator output and having a comparator output; a successive approximation register coupled to the comparator output; and a counter coupled to the comparator output to generate an hybrid analog to digital converter output. The hybrid analog to digital converter may be operable as a successive approximation register converter and a continuous time sigma delta converter.

Abstract: The present disclosure describes a variable gain transconductor having gain and/or linearity performance that are selectively controllable in operation. In one embodiment the gain and/or linearity performance are selectively controllable in response to the strength of an input signal, such as an incoming radio frequency (RF) signal to a radio receiver. In one embodiment, gain and/or linearity performance of the variable gain transconductor are selectively controllable by selecting or deselecting a number of operating bias cells. In one embodiment, gain and/or linearity performance of the variable gain transconductor are selectively controllable by selecting or deselecting a number of operating transconductance (gm) cells. In one embodiment, gain and/or linearity performance of the variable gain transconductor are selectively controllable by selecting or deselecting a combination of operating bias cells and gm cells.

Abstract: Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

Abstract: A dual core crosspoint system includes a differential signal core for receiving N differential input channels with common mode voltage removed and providing m differential output channels with m output stages associated with the m output channels; and a common mode core for receiving N common mode voltage input channels derived from the N differential input channels and providing m common mode voltage output channels simultaneously with the m differential output channels.

Abstract: A MEMS device has a movable beam, a differential capacitor with a movable electrode that moves in response to the displacement of the movable beam and that is disposed between two stationary electrodes, and a voltage circuit for applying a first voltage to the first stationary electrode, second voltage to the second stationary electrode, and a third voltage to the moveable electrode. The MEMS device also has a monitor operably coupled with the movable beam to monitor the displacement of the movable beam. In some embodiments, the monitor may monitor the distance between the movable electrode and at least one of the stationary electrodes. The MEMS device further has a voltage reducing circuit operatively coupled with the monitor, the movable electrode, and the stationary electrodes.