Abstract: Apparatus and methods for pipelined analog-to-digital conversion are disclosed. In some embodiments, a pipeline analog-to-digital converter includes a plurality of multiplying digital-to-analog converter (MDAC) stages coupled in cascade. At least one of the MDAC stages includes two or more flash ADCs connected in parallel, operating alternately to generate digital signals from an analog input voltage. In one embodiment, the flash ADCs provide the digital signals in an alternating manner to a capacitor block that receives a delayed analog input voltage. In another embodiment, the at least one MDAC may include two or more capacitor blocks, each of which is associated with a respective one of the flash ADCs, forming two or more sets of a flash ADC and a capacitor block. In yet another embodiment, the at least one MDAC also include three or more capacitor blocks, each of which can be randomly selected for one of the flash ADCs.

Abstract: Methods and devices for calculating the position of a movable device are disclosed. The device may include multiple optical detectors (ODs) and the movable device may include light sources. Optics may be above the ODs. A controller may calculate the position of the light source based on data from the ODs and properties of the optics. The device may be a game console, and the light source may be a game controller. The roles of the OD and light sources may be interchanged. The rotation of the movable device may be determined using multiple light sources and/or multiple ODs on the movable device. The movable device may calculate its position and transmit it to a console. The light sources may be modulated by time or frequency to distinguish between the light sources. There may be two or more movable devices. There may be two or more consoles.

Abstract: A microphone is formed to have a diaphragm that is configured to improve signal to noise ratio. To that end, the microphone has a backplate having a hole therethrough, and a diaphragm movably coupled with the backplate. The diaphragm has a bottom surface (facing the backplate) with a convex portion aligned with the hole in the backplate.

Abstract: A system for a Class AB Amplifier output stage that includes a first push pull system connected to an output terminal including a first driving transistor coupled to the output terminal and a second push pull system connected to the output terminal including a second driving transistor coupled to the output terminal. The amplifier also includes a current mode amplifier where the current mode amplifier's output is coupled to the first driving transistor's gate. The amplifier further includes a pair of resistors, a first resistor coupled to a first input terminal of the current mode amplifier, a second resistor coupled to a second input terminal of the current mode amplifier and coupled to the second driving transistor.

Abstract: An amplifier circuit can include a first supply terminal to receive a first reference voltage; a second supply terminal to receive a second reference voltage; a first pair of circuit paths extending between the first and second supply terminals and including a respective output terminal, the first pair of circuit paths including a first pair of transistors, each having a gate connected to a respective one of the input terminals and a source connected to the first supply terminal, and a second pair of transistors, each having a gate connected via a first impedance to a gate of a respective first transistor, and a source coupled to the second supply terminal.

Abstract: Data transmitter embodiments are provided which are particularly useful as interface devices for accurate and reliable transmittal of data from high-speed data system devices such as analog-to-digital converters. Transmitter embodiments have been found to provide excellent fidelity of data transfer at high data rates (e.g., 4 gigabits/second) while consuming only a portion of the power of many conventional transmitters and requiring only a portion of the layout area of these transmitters. Transmitter embodiments provide effective control of transmitter parameters such as matched impedances, data symmetry, common-mode level, data eye and current drain.

Abstract: An embodiment of a logarithmic circuit may include a logging transistor, and a multi-tanh circuit arranged to provide temperature compensation to the logging transistor, where the multi-tanh circuit comprises a multiplicity of multi-tanh cells. In another embodiment, a logarithmic circuit may include a logging transistor, and a multi-tanh circuit arranged to provide temperature compensation to the logging transistor, where the multi-tanh circuit includes a first set of outputs arranged to provide an output signal and a second set of one or more outputs that are diverted.

Abstract: A MEMS switch with a platinum-series contact is capped through a process that also passivates the contact by controlling, over time, the amount of oxygen in the environment, pressures and temperatures. Some embodiments passivate a contact in an oxygenated atmosphere at a first temperature and pressure, before hermetically sealing the cap at a higher temperature and pressure. Some embodiments hermetically seal the cap at a temperature below which passivating dioxides will form, thus trapping oxygen within the volume defined by the cap, and later passivate the contact with the trapped oxygen at a higher temperature.

Abstract: A package apparatus has a base coupled with a lid to form a leadframe package. The package has first and second exterior surfaces with respective first and second contact patterns. The first and second contact patterns are substantially electrically identical to permit the package to be either vertically or horizontally mounted to an underlying apparatus.

Abstract: A sink may be to used to process multimedia digital data. The sink may include a plurality of input ports, an output port, a switchably-enabled selector to select an input port from a plurality of HDMI input ports to couple to an output port, a control circuit to detect encrypted data in a channel of the input ports; and a plurality of decryption engines. Each of the decryption engines may be coupled to respective input ports to synchronize with a corresponding encryption engine of a data source after the control circuit detects encrypted data in the channel of the respective input port. Additional circuitry may be included to operate the sink in a power saving mode. Also, methods for processing the data in both power saving and non-power saving modes.

Abstract: A current mirror circuit provided in an emitter follower configuration achieves linearly output over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.

Abstract: A sink may be to used to process multimedia digital data. The sink may include a plurality of input ports, an output port, a switchably-enabled selector to select an input port from a plurality of HDMI input ports to couple to an output port, a control circuit to detect encrypted data in a channel of the input ports; and a plurality of decryption engines. Each of the decryption engines may be coupled to respective input ports to synchronize with a corresponding encryption engine of a data source after the control circuit detects encrypted data in the channel of the respective input port. Additional circuitry may be included to operate the sink in a power saving mode. Also, methods for processing the data in both power saving and non-power saving modes.

Abstract: Apparatus and methods are disclosed, such as those involving a high frequency transmitter. One such apparatus includes a pre-amplifier configured to receive an input signal via an input node; and a capacitor block electrically coupled between the pre-amplifier and an output node from which an output signal is transmitted. The capacitor block is configured to provide charge to the output node or pull charge from the output node while the output signal transitions. The apparatus further includes a switch electrically coupled between the output node and a voltage reference, wherein the switch is turned on or off at least partly in response to a signal from the pre-amplifier. This configuration effectively reduces rise and fall time of the output signal for high-frequency transmission.

Abstract: A sink may be to used to process multimedia digital data. The sink may include a plurality of input ports, an output port, a switchably-enabled selector to select an input port from a plurality of HDMI input ports to couple to an output port, a control circuit to detect encrypted data in a channel of the input ports; and a plurality of decryption engines. Each of the decryption engines may be coupled to respective input ports to synchronize with a corresponding encryption engine of a data source after the control circuit detects encrypted data in the channel of the respective input port. Additional circuitry may be included to operate the sink in a power saving mode. Also, methods for processing the data in both power saving and non-power saving modes.

Abstract: Apparatus and methods for pipelined analog-to-digital conversion are disclosed. In some embodiments, a pipelined analog-to-digital converter includes a control and correction circuit; and a plurality of MDAC stages. At least one of the MDAC stages includes: an MDAC input to receive an analog input voltage; and a dual latch flash ADC comprising one or more dual latch comparators. At least one of the dual latch comparators includes: a pre-amplifier having an input coupled to the MDAC input, and an output; a demultiplexer having an input coupled to the output of the pre-amplifier, a first output, and a second output; a first latch having an input coupled to the first output of the demultiplexer, wherein the first latch may generate a first digital signal; and a second latch having an input coupled to the second output of the demultiplexer, wherein the second latch may generate a second digital signal.

Abstract: A control circuit monitors a signal produced by a MEMS or other capacitor microphone. When a criterion is met, for example when the amplitude of the monitored signal exceeds a threshold or the monitored signal has been clipped or analysis of the monitored signal indicates clipping is imminent or likely, the control circuit automatically adjusts a bias voltage applied to the capacitor microphone, thereby adjusting sensitivity of the capacitor microphone.

Abstract: A microphone is formed to have a diaphragm that is configured to improve signal to noise ratio. To that end, the microphone has a backplate having a hole therethrough, and a diaphragm movably coupled with the backplate. The diaphragm has a bottom surface (facing the backplate) with a convex portion aligned with the hole in the backplate.

Abstract: Apparatus and methods for providing multi-mode clock signals are disclosed. In some embodiments, a multi-mode driver configured to receive a first clock signal, and to selectively output a different clock signal in response to one or more signals from a controller is provided. The driver can include an H-bridge circuit without substantial increases in the size of the design area. Advantageously, lower jitter and improved impedance matching can be accomplished.

Abstract: An N-bit DAC comprises a main DAC circuit having main nodes on which analogue voltages are produced of progressively increasing values in steps of the value of one MSB value, and a sub-DAC circuit having secondary nodes on which analogue voltages are produced of progressively increasing values in steps of the value of one LSB. A main switch network couples the secondary nodes to a selected pair of main nodes as the MSB value of the digital input signal varies. A secondary switch network selectively couples one of secondary nodes to an output terminal for providing an analogue voltage output signal. The main nodes are coupled between main terminals, and a voltage reference is applied across input terminals. A first offset circuit and a first compensating circuit are selectively coupleable between the main DAC circuit and the input terminals for offsetting the main node analogue voltages downwardly.

Abstract: A MEMS device has a movable beam, a differential capacitor with a movable electrode that moves in response to the displacement of the movable beam and that is disposed between two stationary electrodes, and a voltage circuit for applying a first voltage to the first stationary electrode, second voltage to the second stationary electrode, and a third voltage to the movable electrode. The MEMS device also has a monitor operably coupled with the movable beam to monitor the displacement of the movable beam. In some embodiments, the monitor may monitor the distance between the movable electrode and at least one of the stationary electrodes. The MEMS device further has a voltage reducing circuit operatively coupled with the monitor, the movable electrode, and the stationary electrodes.